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426 Publications
2021 | Conference Paper | LibreCat-ID: 21610
M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis,” in Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021, Virtual, 2021, pp. 27–32.
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2021 | Bachelorsthesis | LibreCat-ID: 22216
J. W. Rehnen, Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib. 2021.
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2021 | Conference Paper | LibreCat-ID: 22309
M. Awais and M. Platzner, “MCTS-Based Synthesis Towards Efficient Approximate Accelerators,” in Proceedings of IEEE Computer Society Annual Symposium on VLSI, Tampa, Florida USA (Virtual), 2021, pp. 384–389.
LibreCat
2021 | Bachelorsthesis | LibreCat-ID: 22483
M. Brede, Implementation and Profiling of XCS in the Context of Embedded Systems. Paderborn: Paderborn University, 2021.
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2021 | Conference Paper | LibreCat-ID: 21953
L. M. Witschen, T. Wiersema, M. Raeisi Nafchi, A. Bockhorn, and M. Platzner, “Timing Optimization for Virtual FPGA Configurations,” in Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21), Virtual conference, doi: 10.1007/978-3-030-79025-7_4.
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2021 | Journal Article | LibreCat-ID: 30906
A. Boschmann, D. Neuhaus, S. Vogt, C. Kaltschmidt, M. Platzner, and S. Dosen, “Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis,” Journal of NeuroEngineering and Rehabilitation, vol. 18, no. 1, Art. no. 25, 2021, doi: 10.1186/s12984-021-00822-6.
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2021 | Journal Article | LibreCat-ID: 30907
A. Rodriguez, A. Otero, M. Platzner, and E. De la Torre, “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs,” IEEE Transactions on Computers, pp. 1–1, 2021, doi: 10.1109/tc.2021.3107196.
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2021 | Conference Paper | LibreCat-ID: 29137
T. Hansmeier, “Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS,” presented at the International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART ’21), Online, 2021, doi: 10.1145/3468044.3468055.
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2021 | Mastersthesis | LibreCat-ID: 29540
M. A. Sheikh, Design and Implementation of a ReconROS-based Obstacle Avoidance System. Paderborn University, 2021.
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2021 | Preprint | LibreCat-ID: 22764 |
C. Lienen and M. Platzner, “Design of Distributed Reconfigurable Robotics Systems with ReconROS,” arXiv:2107.07208. 2021.
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2021 | Conference Paper | LibreCat-ID: 21813
T. Hansmeier and M. Platzner, “An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS,” in GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Lille, France, 2021, pp. 1639–1647, doi: 10.1145/3449726.3463159.
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2021 | Journal Article | LibreCat-ID: 27841
M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, and T. Wiersema, “Software/Hardware Co-Verification for Custom Instruction Set Processors,” IEEE Access, 2021, doi: 10.1109/ACCESS.2021.3131213.
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2021 | Conference Paper | LibreCat-ID: 29138
Q. A. Ahmed, “Hardware Trojans in Reconfigurable Computing,” 2021, doi: 10.1109/vlsi-soc53125.2021.9606974.
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2021 | Conference Paper | LibreCat-ID: 20681 |
Q. A. Ahmed, T. Wiersema, and M. Platzner, “Malicious Routing: Circumventing Bitstream-level Verification for FPGAs,” presented at the Design, Automation and Test in Europe Conference (DATE’21), Alpexpo | Grenoble, France, 2021, doi: 10.23919/DATE51398.2021.9474026.
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2021 | Conference Paper | LibreCat-ID: 30909
L. Clausing, “ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip,” 2021, doi: 10.1145/3468044.3468056.
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2021 | Conference Paper | LibreCat-ID: 30908
H. Ghasemzadeh Mohammadi et al., “FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics,” 2021, doi: https://doi.org/10.1007/978-3-030-93736-2_27.
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2020 | Conference Paper | LibreCat-ID: 3583
Z. Guetttatfi, P. Kaufmann, and M. Platzner, “Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices,” in Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC), 2020.
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2020 | Mastersthesis | LibreCat-ID: 21324
K. Chandrakar, Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis. 2020.
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2020 | Bachelorsthesis | LibreCat-ID: 21432
L.-S. Henke, Evaluation of a ReconOS-ROS Combination based on a Video Processing Application. 2020.
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2020 | Journal Article | LibreCat-ID: 17369
N. Ho, P. Kaufmann, and M. Platzner, “Evolution of Application-Specific Cache Mappings,” International Journal of Hybrid intelligent Systems, 2020.
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2020 | Preprint | LibreCat-ID: 20748
L. M. Witschen, T. Wiersema, and M. Platzner, “Search Space Characterization for AxC Synthesis,” Fifth Workshop on Approximate Computing (AxC 2020). .
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2020 | Conference Paper | LibreCat-ID: 20750
C. Lienen, M. Platzner, and B. Rinner, “ReconROS: Flexible Hardware Acceleration for ROS2 Applications,” in Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT), 2020.
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2020 | Bachelorsthesis | LibreCat-ID: 20820
S. Thiele, Implementing Machine Learning Functions as PYNQ FPGA Overlays. 2020.
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2020 | Mastersthesis | LibreCat-ID: 20821
V. Jaganath, Extension and Evaluation of Python-based High-Level Synthesis Tool Flows. 2020.
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2020 | Conference Paper | LibreCat-ID: 17063
T. Hansmeier, P. Kaufmann, and M. Platzner, “An Adaption Mechanism for the Error Threshold of XCSF,” in GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Cancún, Mexico, 2020, pp. 1756–1764, doi: 10.1145/3377929.3398106.
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2020 | Journal Article | LibreCat-ID: 15836
K. Bellman et al., “Self-aware Cyber-Physical Systems,” ACM Transactions on Cyber-Physical Systems, vol. Accepted for Publication, pp. 1–24, 2020.
LibreCat
2020 | Conference Paper | LibreCat-ID: 16363
T. Hansmeier, P. Kaufmann, and M. Platzner, “Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold,” in GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Cancún, Mexico, 2020, pp. 125–126.
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2020 | Conference Paper | LibreCat-ID: 20838
A. Lösch and M. Platzner, “MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes,” 2020, doi: 10.1109/ipdpsw50202.2020.00012.
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| DOI
2020 | Mastersthesis | LibreCat-ID: 21433
F. P. Jentzsch, Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture. 2020.
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2019 | Preprint | LibreCat-ID: 16853
L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits,” Fourth Workshop on Approximate Computing (AxC 2019). .
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2019 | Conference Paper | LibreCat-ID: 10577
L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits,” in Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19, Tysons Corner, VA, USA, 2019.
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2019 | Conference Paper | LibreCat-ID: 15422
N. Ho, P. Kaufmann, and M. Platzner, “Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor,” in World Congress on Nature and Biologically Inspired Computing (NaBIC), 2019.
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2019 | Mastersthesis | LibreCat-ID: 15883
S. Kumar Jeyakumar, Incremental learning with Support Vector Machine on embedded platforms. 2019.
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2019 | Mastersthesis | LibreCat-ID: 15920
M. Keerthipati, A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking. Universität Paderborn, 2019.
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2019 | Mastersthesis | LibreCat-ID: 14831
N. S. Sabu, FPGA Acceleration of String Search Techniques in Huge Data Sets. Paderborn University, 2019.
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2019 | Mastersthesis | LibreCat-ID: 15946
J. Mehta, Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Recongurable System-on-Chip. 2019.
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2019 | Mastersthesis | LibreCat-ID: 14546
T. Hansmeier, Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers. Universität Paderborn, 2019.
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2019 | Conference Paper | LibreCat-ID: 31067
Z. Guettatfi, M. Platzner, O. Kermia, and A. Khouas, “An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware,” 2019, doi: 10.1109/ipdpsw.2019.00027.
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| DOI
2019 | Conference Paper | LibreCat-ID: 9913 |
Q. A. Ahmed, T. Wiersema, and M. Platzner, “Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan,” in Applied Reconfigurable Computing, Darmstadt, Germany, 2019, vol. 11444, pp. 127–136, doi: 10.1007/978-3-030-17227-5_10.
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2019 | Mastersthesis | LibreCat-ID: 15874 |
C. Lienen, Implementing a Real-time System on a Platform FPGA operated with ReconOS. Universität Paderborn.
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2019 | Journal Article | LibreCat-ID: 12871 |
M. Platzner and C. Plessl, “FPGAs im Rechenzentrum,” Informatik Spektrum, 2019, doi: 10.1007/s00287-019-01187-w.
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2019 | Mastersthesis | LibreCat-ID: 52478
J. D. Mehta, Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfigurable System-on-Chip. 2019.
LibreCat
2018 | Conference Paper | LibreCat-ID: 3362
A. Lösch, A. Wiens, and M. Platzner, “Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes,” in Proceedings of the International Conference on Architecture of Computing Systems (ARCS), 2018, vol. 10793, pp. 73–84.
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