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449 Publications


2010 | Conference Paper | LibreCat-ID: 10776
Sub-threshold charge recovery circuits
M. Khatir, H. Ghasemzadeh Mohammadi, A. Ejlali, in: Computer Design (ICCD), 2010 IEEE International Conference On, IEEE, 2010, pp. 138–144.
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2010 | Conference Paper | LibreCat-ID: 13640
A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier
H. Giefers, M. Platzner, in: Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2010.
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2010 | Conference Paper | LibreCat-ID: 13641
Engineering Self-Coordinating Software Intensive Systems
W. Schäfer, M. Birattari, J. Blömer, M. Dorigo, G. Engels, R. O’Grady, M. Platzner, F.-J. Rammig, W. Reif, A. Trächtler, in: Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER), 2010, pp. 321–324.
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2010 | Conference Paper | LibreCat-ID: 13642
A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics
H. Giefers, M. Platzner, in: Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010.
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2010 | Conference Paper | LibreCat-ID: 2223
Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware
E. Lübbers, M. Platzner, C. Plessl, A. Keller, B. Plattner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 225–231.
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2010 | Conference Paper | LibreCat-ID: 2216
Pruning the Design Space for Just-In-Time Processor Customization
M. Grad, C. Plessl, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2010, pp. 67–72.
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2010 | Conference Paper | LibreCat-ID: 2224
An Open Source Circuit Library with Benchmarking Facilities
M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 144–150.
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2010 | Conference Paper | LibreCat-ID: 2220
Configurable Processor Architectures: History and Trends
D. Andrews, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, p. 165.
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2010 | Conference (Editor) | LibreCat-ID: 2222
Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)
T.P. Plaks, D. Andrews, R. DeMara, H. Lam, J. Lee, C. Plessl, G. Stitt, eds., Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010.
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2010 | Conference Paper | LibreCat-ID: 2226
Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators
T. Beisel, M. Niekamp, C. Plessl, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010, pp. 65–72.
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2010 | Conference Paper | LibreCat-ID: 2206
Reconfigurable Nodes for Future Networks
A. Keller, B. Plattner, E. Lübbers, M. Platzner, C. Plessl, in: Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp. 372–376.
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2010 | Conference Paper | LibreCat-ID: 2228
Performance Estimation for the Exploration of CPU-Accelerator Architectures
T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: O. Hammami, S. Larrabee (Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), 2010.
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2009 | Conference Paper | LibreCat-ID: 10639
Towards multi-movement hand prostheses: Combining adaptive classification with high precision sockets
A. Boschmann, P. Kaufmann, M. Platzner, M. Winkler, in: Proc. Technically Assisted Rehabilitation (TAR), 2009.
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2009 | Mastersthesis | LibreCat-ID: 10702
Evolvable Robot Controller
A. Kostin, Evolvable Robot Controller, Paderborn University, 2009.
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2009 | Journal Article | LibreCat-ID: 10703
ReconOS: Multithreaded Programming for Reconfigurable Computers
E. Lübbers, M. Platzner, ACM Transactions on Embedded Computing Systems 9 (2009) 8:1-8:33.
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2009 | Mastersthesis | LibreCat-ID: 10746
Compiler for a Custom Instruction Set CPU
M. Tofall, Compiler for a Custom Instruction Set CPU, Paderborn University, 2009.
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2009 | Mastersthesis | LibreCat-ID: 10749
Coarse-grained CGP Model using Xilinx Virtex5 DSP48E Functional Units
A. Warkentin, Coarse-Grained CGP Model Using Xilinx Virtex5 DSP48E Functional Units, Paderborn University, 2009.
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2009 | Bachelorsthesis | LibreCat-ID: 10753
Implementierung von Kryptographie-Hardwarebeschleunigern für das HW/SW-Betriebssystem ReconOS
B. Wildenhain, Implementierung von Kryptographie-Hardwarebeschleunigern Für Das HW/SW-Betriebssystem ReconOS, Paderborn University, 2009.
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2009 | Conference Paper | LibreCat-ID: 10777
Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors
H. Ghasemzadeh Mohammadi, S.G. Miremadi, A. Ejlali, in: Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium On, IEEE, 2009, pp. 252–255.
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2009 | Conference Paper | LibreCat-ID: 13632
A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms
M. Happe, E. Lübbers, M. Platzner, in: Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC), Springer, 2009.
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