Tradeoff analysis and architecture design of a hybrid hardware/software sorter
M. Bednara, O. Beyer, J. Teich, R. Wanka, in: Proc. Int. Conf. on Application Specific Systems, Architectures, and Processors (ASAP), 2000, pp. 299–308.
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Conference Paper
| Published
| English
Author
Bednara, M.;
Beyer, O.;
Teich, J.;
Wanka, Rolf
Publishing Year
Proceedings Title
Proc. Int. Conf. on Application Specific Systems, Architectures, and Processors (ASAP)
Page
299-308
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Bednara M, Beyer O, Teich J, Wanka R. Tradeoff analysis and architecture design of a hybrid hardware/software sorter. In: Proc. Int. Conf. on Application Specific Systems, Architectures, and Processors (ASAP). ; 2000:299-308. doi:10.1109/asap.2000.862400
Bednara, M., Beyer, O., Teich, J., & Wanka, R. (2000). Tradeoff analysis and architecture design of a hybrid hardware/software sorter. Proc. Int. Conf. on Application Specific Systems, Architectures, and Processors (ASAP), 299–308. https://doi.org/10.1109/asap.2000.862400
@inproceedings{Bednara_Beyer_Teich_Wanka_2000, title={Tradeoff analysis and architecture design of a hybrid hardware/software sorter}, DOI={10.1109/asap.2000.862400}, booktitle={Proc. Int. Conf. on Application Specific Systems, Architectures, and Processors (ASAP)}, author={Bednara, M. and Beyer, O. and Teich, J. and Wanka, Rolf}, year={2000}, pages={299–308} }
Bednara, M., O. Beyer, J. Teich, and Rolf Wanka. “Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter.” In Proc. Int. Conf. on Application Specific Systems, Architectures, and Processors (ASAP), 299–308, 2000. https://doi.org/10.1109/asap.2000.862400.
M. Bednara, O. Beyer, J. Teich, and R. Wanka, “Tradeoff analysis and architecture design of a hybrid hardware/software sorter,” in Proc. Int. Conf. on Application Specific Systems, Architectures, and Processors (ASAP), 2000, pp. 299–308, doi: 10.1109/asap.2000.862400.
Bednara, M., et al. “Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter.” Proc. Int. Conf. on Application Specific Systems, Architectures, and Processors (ASAP), 2000, pp. 299–308, doi:10.1109/asap.2000.862400.
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