Heteroepitaxy of III–V Zinc Blende Semiconductors on Nanopatterned Substrates

In the last decade, zinc blende structure III–V semiconductors have been increasingly utilized for the realization of high‐performance optoelectronic applications because of their tunable bandgaps, high carrier mobility and the absence of piezoelectric fields. However, the integration of III–V devices on the Si platform commonly used for CMOS electronic circuits still poses a challenge, due to the large densities of mismatch‐related defects in heteroepitaxial III–V layers grown on planar Si substrates. A promising method to obtain thin III–V layers of high crystalline quality is the growth on nanopatterned substrates. In this approach, defects can be effectively eliminated by elastic lattice relaxation in three dimensions or confined close to the substrate interface by using aspect‐ratio trapping masks. As a result, an etch pit density as low as 3.3 × 10^5 cm^−2 and a flat surface of submicron GaAs layers have been accomplished by growth onto a SiO2 nanohole film patterned Si(001) substrate, where the threading defects are trapped at the SiO2 mask sidewalls. An open issue that remains to be resolved is to gain a better understanding of the interplay between mask shape, growth conditions and formation of coalescence defects during mask overgrowth in order to achieve thin device quality III–V layers