A Computation of the Ninth Dedekind Number Using FPGA Supercomputing

L. Van Hirtum, P. De Causmaecker, J. Goemaere, T. Kenter, H. Riebler, M. Laß, C. Plessl, ACM Transactions on Reconfigurable Technology and Systems 17 (2024) 1–28.

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Abstract
<jats:p> This manuscript makes the claim of having computed the <jats:inline-formula content-type="math/tex"> <jats:tex-math notation="LaTeX" version="MathJax">\(9\)</jats:tex-math> </jats:inline-formula> th Dedekind number, D(9). This was done by accelerating the core operation of the process with an efficient FPGA design that outperforms an optimized 64-core CPU reference by 95 <jats:inline-formula content-type="math/tex"> <jats:tex-math notation="LaTeX" version="MathJax">\(\times\)</jats:tex-math> </jats:inline-formula> . The FPGA execution was parallelized on the Noctua 2 supercomputer at Paderborn University. The resulting value for D(9) is 286386577668298411128469151667598498812366. This value can be verified in two steps. We have made the data file containing the 490 M results available, each of which can be verified separately on CPU, and the whole file sums to our proposed value. The paper explains the mathematical approach in the first part, before putting the focus on a deep dive into the FPGA accelerator implementation followed by a performance analysis. The FPGA implementation was done in Register-Transfer Level using a dual-clock architecture and shows how we achieved an impressive FMax of 450 MHz on the targeted Stratix 10 GX 2,800 FPGAs. The total compute time used was 47,000 FPGA hours. </jats:p>
Publishing Year
Journal Title
ACM Transactions on Reconfigurable Technology and Systems
Volume
17
Issue
3
Page
1-28
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Van Hirtum L, De Causmaecker P, Goemaere J, et al. A Computation of the Ninth Dedekind Number Using FPGA Supercomputing. ACM Transactions on Reconfigurable Technology and Systems. 2024;17(3):1-28. doi:10.1145/3674147
Van Hirtum, L., De Causmaecker, P., Goemaere, J., Kenter, T., Riebler, H., Laß, M., & Plessl, C. (2024). A Computation of the Ninth Dedekind Number Using FPGA Supercomputing. ACM Transactions on Reconfigurable Technology and Systems, 17(3), 1–28. https://doi.org/10.1145/3674147
@article{Van Hirtum_De Causmaecker_Goemaere_Kenter_Riebler_Laß_Plessl_2024, title={A Computation of the Ninth Dedekind Number Using FPGA Supercomputing}, volume={17}, DOI={10.1145/3674147}, number={3}, journal={ACM Transactions on Reconfigurable Technology and Systems}, publisher={Association for Computing Machinery (ACM)}, author={Van Hirtum, Lennart and De Causmaecker, Patrick and Goemaere, Jens and Kenter, Tobias and Riebler, Heinrich and Laß, Michael and Plessl, Christian}, year={2024}, pages={1–28} }
Van Hirtum, Lennart, Patrick De Causmaecker, Jens Goemaere, Tobias Kenter, Heinrich Riebler, Michael Laß, and Christian Plessl. “A Computation of the Ninth Dedekind Number Using FPGA Supercomputing.” ACM Transactions on Reconfigurable Technology and Systems 17, no. 3 (2024): 1–28. https://doi.org/10.1145/3674147.
L. Van Hirtum et al., “A Computation of the Ninth Dedekind Number Using FPGA Supercomputing,” ACM Transactions on Reconfigurable Technology and Systems, vol. 17, no. 3, pp. 1–28, 2024, doi: 10.1145/3674147.
Van Hirtum, Lennart, et al. “A Computation of the Ninth Dedekind Number Using FPGA Supercomputing.” ACM Transactions on Reconfigurable Technology and Systems, vol. 17, no. 3, Association for Computing Machinery (ACM), 2024, pp. 1–28, doi:10.1145/3674147.
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