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282 Publications
2023 | Conference Paper | LibreCat-ID: 48530
W. Müller, M. Ulbricht, L. Li, and M. Krstic, “Der TETRISC SoC - Ein resilientes Quad-Core System auf Pulpissimo-Basis,” presented at the 5. ITG / GMM / GI -Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen , Erfurt. Germany, 2023.
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2023 | Conference Abstract | LibreCat-ID: 48961
M. Iftekhar, H. Gowda, P. Kneuper, B. Sadiye, W. Müller, and C. Scheytt, “A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology,” presented at the 2023 IEEE BiCMOS und Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), Monterey, CA, USA, 2023, doi: 10.1109/BCICTS54660.2023.10310954.
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2023 | Conference Paper | LibreCat-ID: 45775
L. Luchterhandt et al., “Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture,” presented at the MBMV 2023, Freiburg, Freiburg, 2023.
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2023 | Conference Abstract | LibreCat-ID: 47064
M. Iftekhar, H. Nagaraju, P. Kneuper, B. Sadiye, W. Müller, and J. C. Scheytt, “A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology ,” MONTEREY, CALIFORNIA, USA, 2023.
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2022 | Conference Paper | LibreCat-ID: 29302
W. Ecker et al., “The Scale4Edge RISC-V Ecosystem,” 2022.
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2021 | Conference Paper | LibreCat-ID: 32125
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules,” 2021.
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2021 | Conference Paper | LibreCat-ID: 32132
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “QEMU zur Simulation von Worst-Case-Ausführungszeiten,” 2021.
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2021 | Conference Paper | LibreCat-ID: 23992
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules,” 2021.
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2020 | Conference Paper | LibreCat-ID: 24027
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures,” 2020.
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2019 | Conference Paper | LibreCat-ID: 24058
B. Koppelmann, P. Adelt, W. Müller, and C. Scheytt, “RISC-V Extensions for Bit Manipulation Instructions,” 2019, doi: 10.1109/PATMOS.2019.8862170.
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2019 | Conference Paper | LibreCat-ID: 24060
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Analyse sicherheitskritischer Software für RISC-V Prozessoren,” 2019.
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2019 | Conference Paper | LibreCat-ID: 24061
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, and B. Driessen, “QEMU for Dynamic Memory Analysis of Security Sensitive Software,” in 2nd International Workshop on Embedded Software for Industrial IoT in conjunction with DATE 2019, 2019, pp. 32–34.
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2019 | Journal Article | LibreCat-ID: 24063
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “QEMU Support for RISC-V: Current State and Future Releases,” 2nd International Workshop on RISC-V Research Activities, vol. (Presentation), 2019.
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2019 | Book (Editor) | LibreCat-ID: 53596
O. Bringmann, W. Ecker, W. Müller, and D. Müller-Gridschneder, Eds., Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT. Florence, Italy, 2019.
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2018 | Journal Article | LibreCat-ID: 24194
P. Adelt, B. Koppelmann, and W. Müller, “Current and Future RISC-V Activities for Virtual Prototyping and Chip Design,” International Workshop on RISC-V Research Activities, vol. Presentation, 2018.
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2018 | Conference Paper | LibreCat-ID: 24196
L. Wu, M. K. Hussain, S. Abughannam, W. Müller, C. Scheytt, and W. Ecker, “Analog fault simulation automation at schematic level with random sampling techniques,” 2018, doi: 10.1109/DTIS.2018.8368549.
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2018 | Book (Editor) | LibreCat-ID: 53595
O. Bringmann, W. Ecker, W. Müller, and D. Müller-Gridschneder, Eds., Proceedings of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT. Dresden, Germany, 2018.
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2017 | Conference Paper | LibreCat-ID: 24220
P. Adelt, B. Koppelmann, W. Müller, D. Mueller-Gritschneder, B. Kleinjohann, and C. Scheytt, “Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen,” 2017, doi: 10.17619/UNIPB/1-93.
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2017 | Conference Paper | LibreCat-ID: 24223
L. Wu, S. Abughannam, W. Müller, C. Scheytt, and W. Ecker, “SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study,” in 2nd Workshop on Resiliency in Embedded Electronic Systems (REES), 2017, p. 68.
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2017 | Conference Paper | LibreCat-ID: 24224
P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, and C. Scheytt, “ANALISA - A Tool for Static Instruction Set Analysis,” 2017.
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