RISC-V Extensions for Bit Manipulation Instructions
B. Koppelmann, P. Adelt, W. Müller, C. Scheytt, in: 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Rhodos, Griechenland, 2019.
Download
No fulltext has been uploaded.
Conference Paper
| English
Author
Abstract
Embedded systems require a high energy efficiency in combination with an optimized performance. As such, Bit Manipulation Instructions (BMIs) were introduced for x86 and ARMv8 to improve the runtime efficiency and power dissipation of the compiled software for various applications. Though the RISC-V platform is meanwhile widely accepted for embedded systems application, its instruction set architecture (ISA) currently still supports only two basic BMIs.We introduce ten advanced BMIs for the RISC-V ISA and implemented them on Berkeley's Rocket CPU [1], which we synthesized for the Artix-7 FPGA and the TSMC 65nm cell library. Our RISC-V BMI definitions are based on an analysis and combination of existing x86 and ARMv8 BMIs. Our Rocket CPU hardware extensions show that RISC-V BMI extensions have no negative impact on the critical path of the execution pipeline. Our software evaluations show that we can, for example, expect a significant impact for time and power consuming cryptographic applications.
Publishing Year
Proceedings Title
29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)
Conference Date
2019.07.01 – 2019.07.03
LibreCat-ID
Cite this
Koppelmann B, Adelt P, Müller W, Scheytt C. RISC-V Extensions for Bit Manipulation Instructions. In: 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS). ; 2019. doi:10.1109/PATMOS.2019.8862170
Koppelmann, B., Adelt, P., Müller, W., & Scheytt, C. (2019). RISC-V Extensions for Bit Manipulation Instructions. 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS). https://doi.org/10.1109/PATMOS.2019.8862170
@inproceedings{Koppelmann_Adelt_Müller_Scheytt_2019, place={Rhodos, Griechenland}, title={RISC-V Extensions for Bit Manipulation Instructions}, DOI={10.1109/PATMOS.2019.8862170}, booktitle={29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)}, author={Koppelmann, Bastian and Adelt, Peer and Müller, Wolfgang and Scheytt, Christoph}, year={2019} }
Koppelmann, Bastian, Peer Adelt, Wolfgang Müller, and Christoph Scheytt. “RISC-V Extensions for Bit Manipulation Instructions.” In 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS). Rhodos, Griechenland, 2019. https://doi.org/10.1109/PATMOS.2019.8862170.
B. Koppelmann, P. Adelt, W. Müller, and C. Scheytt, “RISC-V Extensions for Bit Manipulation Instructions,” 2019, doi: 10.1109/PATMOS.2019.8862170.
Koppelmann, Bastian, et al. “RISC-V Extensions for Bit Manipulation Instructions.” 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2019, doi:10.1109/PATMOS.2019.8862170.
Google Scholar