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18 Publications
2022 | Conference Paper | LibreCat-ID: 29302
W. Ecker et al., “The Scale4Edge RISC-V Ecosystem,” 2022.
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2021 | Conference Paper | LibreCat-ID: 32125
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules,” 2021.
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2021 | Conference Paper | LibreCat-ID: 32132
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “QEMU zur Simulation von Worst-Case-Ausführungszeiten,” 2021.
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2021 | Conference Paper | LibreCat-ID: 23992
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules,” 2021.
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2020 | Conference Paper | LibreCat-ID: 24027
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures,” 2020.
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2019 | Conference Paper | LibreCat-ID: 24058
B. Koppelmann, P. Adelt, W. Müller, and C. Scheytt, “RISC-V Extensions for Bit Manipulation Instructions,” 2019, doi: 10.1109/PATMOS.2019.8862170.
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2019 | Conference Paper | LibreCat-ID: 24060
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Analyse sicherheitskritischer Software für RISC-V Prozessoren,” 2019.
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2019 | Conference Paper | LibreCat-ID: 24061
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, and B. Driessen, “QEMU for Dynamic Memory Analysis of Security Sensitive Software,” in 2nd International Workshop on Embedded Software for Industrial IoT in conjunction with DATE 2019, 2019, pp. 32–34.
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2019 | Journal Article | LibreCat-ID: 24063
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “QEMU Support for RISC-V: Current State and Future Releases,” 2nd International Workshop on RISC-V Research Activities, vol. (Presentation), 2019.
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2018 | Journal Article | LibreCat-ID: 24194
P. Adelt, B. Koppelmann, and W. Müller, “Current and Future RISC-V Activities for Virtual Prototyping and Chip Design,” International Workshop on RISC-V Research Activities, vol. Presentation, 2018.
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2017 | Conference Paper | LibreCat-ID: 24220
P. Adelt, B. Koppelmann, W. Müller, D. Mueller-Gritschneder, B. Kleinjohann, and C. Scheytt, “Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen,” 2017, doi: 10.17619/UNIPB/1-93.
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2017 | Conference Paper | LibreCat-ID: 24224
P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, and C. Scheytt, “ANALISA - A Tool for Static Instruction Set Analysis,” 2017.
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2017 | Conference Paper | LibreCat-ID: 24225
P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, and C. Scheytt, “An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries,” in 2nd Workshop on Resiliency in Embedded Electronic Systems (REES) , 2017, p. 44.
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2017 | Conference Paper | LibreCat-ID: 25068
P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, and J. C. Scheytt, “ANALISA - A Tool for Static Instruction Set Analysis,” in Design Automation and Testing in Europe (DATE), Lausanne, CH, Mrz. 2017, 2017.
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2017 | Conference Paper | LibreCat-ID: 25069
P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, and J. C. Scheytt, “ANALISA - A Tool for Static Instruction Set Analysis,” in Design Automation and Testing in Europe (DATE), Lausanne, CH, Mrz. 2017, 2017.
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2016 | Conference Paper | LibreCat-ID: 24264
P. Adelt, B. Koppelmann, W. Müller, M. Becker, B. Kleinjohann, and C. Scheytt, “Fast Dynamic Fault Injection for Virtual Microcontroller Platforms,” 2016, doi: 10.1109/VLSI-SoC.2016.7753545.
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2016 | Conference Paper | LibreCat-ID: 24269
J. Jatzkowski, P. Adelt, and A. Rettberg, “Hierarchical Scheduling for Plug-and-Produce,” in 3rd International Conference on System-integrated Intelligence: New Challenges for Product and Production Engineering, 2016, pp. 227–234, doi: 10.1016/j.protcy.2016.08.031.
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2015 | Mastersthesis | LibreCat-ID: 24288
P. Adelt, Analyse von Ausführungszeiten durch Integration einer statischen WCET-Analyse mit einer dynamischen Befehlssatzsimulation am Beispiel der TriCore-Architektur. Universität Paderborn, Fakultät EIM, 2015.
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