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92 Publications


2016 | Conference Paper | LibreCat-ID: 168
Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. In: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE). EDA Consortium / IEEE; 2016:912-917.
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2016 | Conference Paper | LibreCat-ID: 171
Kenter T, Vaz GF, Riebler H, Plessl C. Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). In: Workshop on Reconfigurable Computing (WRC). ; 2016.
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2015 | Bachelorsthesis | LibreCat-ID: 3364
Knorr C. Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn; 2015.
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2015 | Journal Article | LibreCat-ID: 1772
Torresen J, Plessl C, Yao X. Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer. 2015;48(7):18-20. doi:10.1109/MC.2015.205
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2015 | Mastersthesis | LibreCat-ID: 5413
Funke L. An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications Using FPGA Overlay Architectures. Universität Paderborn; 2015.
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2015 | Mastersthesis | LibreCat-ID: 5416
Löcke T. Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems. Universität Paderborn; 2015.
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2015 | Mastersthesis | LibreCat-ID: 5419
Wallaschek F. Accelerating Programmable Logic Controllers with the Use of FPGAs. Universität Paderborn; 2015.
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2015 | Journal Article | LibreCat-ID: 296
Kenter T, Schmitz H, Plessl C. Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International Journal of Reconfigurable Computing (IJRC). 2015;2015. doi:10.1155/2015/859425
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2015 | Conference Paper | LibreCat-ID: 303 | OA
Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. In: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT). ; 2015.
LibreCat | Files available | arXiv
 

2015 | Conference Paper | LibreCat-ID: 238
Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational hotspots from binary code to Xeon Phi. In: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE). EDA Consortium / IEEE; 2015:1078-1083. doi:10.7873/DATE.2015.1124
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2014 | Bachelorsthesis | LibreCat-ID: 334
Wagener P. Vertical Thread Migration in FPGA Based Sound Localization. Universität Paderborn; 2014.
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2014 | Conference Paper | LibreCat-ID: 347
Meisner S, Platzner M. Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection. In: Goehringer D, Santambrogio M, Cardoso JP, Bertels K, eds. Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC). Lecture Notes in Computer Science. Springer; 2014:283-290. doi:10.1007/978-3-319-05960-0_30
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2014 | Bachelorsthesis | LibreCat-ID: 348
Rüthing C. The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores. Universität Paderborn; 2014.
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2014 | Conference Paper | LibreCat-ID: 368
Brinkmann A, Kling P, Meyer auf der Heide F, Nagel L, Riechers S, Suess T. Scheduling Shared Continuous Resources on Many-Cores. In: Proceedings of the 26th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA). ; 2014:128-137. doi:10.1145/2612669.2612698
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2014 | Conference Paper | LibreCat-ID: 374
Wold A, Agne A, Torresen J. Relocatable Hardware Threads in Run-Time Reconfigurable Systems. In: Goehringer D, Santambrogio M, Cardoso JP, Bertels K, eds. Proceedings of the 10th International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications. LNCS. ; 2014:61-72. doi:10.1007/978-3-319-05960-0_6
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2014 | Conference Paper | LibreCat-ID: 451
Drees M, Riechers S, Skopalik A. Budget-restricted utility games with ordered strategic decisions. In: Lavi R, ed. Proceedings of the 7th International Symposium on Algorithmic Game Theory (SAGT). Lecture Notes in Computer Science. ; 2014:110-121. doi:10.1007/978-3-662-44803-8_10
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2014 | Mastersthesis | LibreCat-ID: 460
Mittendorf R. Advanced AES-Key Recovery from Decayed RAM-Dumps Using Multi-Threading and FPGAs. Universität Paderborn; 2014.
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2014 | Mastersthesis | LibreCat-ID: 466
Brand M. A Generalized Loop Accelerator Implemented as a Coarse Grained Array. Universität Paderborn; 2014.
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2014 | Dissertation | LibreCat-ID: 431
Kling P. Energy-Efficient Scheduling Algorithms. Universität Paderborn; 2014.
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2014 | Conference Paper | LibreCat-ID: 435
Antoniadis A, Barcelo N, Consuegra M, et al. Efficient Computation of Optimal Energy and Fractional Weighted Flow Trade-off Schedules. In: Proceedings of the 31st Symposium on Theoretical Aspects of Computer Science (STACS). LIPIcs. ; 2014:63--74. doi:10.4230/LIPIcs.STACS.2014.63
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