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226 Publications
2003 | Conference Paper | LibreCat-ID: 13615
Steiger C, Walder H, Platzner M. Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices. In: Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL). Berlin, Heidelberg: Springer; 2003:575-584. doi:10.1007/978-3-540-45234-8_56
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| DOI
2003 | Conference Paper | LibreCat-ID: 13617
Steiger C, Walder H, Platzner M, Thiele L. Online scheduling and placement of real-time tasks to partially reconfigurable devices. In: Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS). IEEE CS Press; 2003:252-235. doi:10.1109/real.2003.1253269
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| DOI
2002 | Conference Paper | LibreCat-ID: 2423
Plessl C, Enzler R, Walder H, Beutel J, Platzner M, Thiele L. Reconfigurable Hardware in Wearable Computing Nodes. In: Proc. Int. Symp. on Wearable Computers (ISWC). IEEE Computer Society; 2002:215-222. doi:10.1109/ISWC.2002.1167250
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| DOI
2002 | Conference Paper | LibreCat-ID: 2424
Dyer M, Plessl C, Platzner M. Partially Reconfigurable Cores for Xilinx Virtex. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). Vol 2438. Lecture Notes in Computer Science (LNCS). Springer; 2002:292-301. doi:10.1007/3-540-46117-5
LibreCat
| DOI
2002 | Conference Paper | LibreCat-ID: 2425
Plessl C, Platzner M. Custom Computing Machines for the Set Covering Problem. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer Society; 2002:163-172. doi:10.1109/FPGA.2002.1106671
LibreCat
| DOI
2002 | Conference Paper | LibreCat-ID: 13611
Walder H, Platzner M. Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform. In: Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2002:24-30.
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2001 | Conference Paper | LibreCat-ID: 2428
Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2001:85-91.
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2001 | Conference Paper | LibreCat-ID: 2432
Enzler R, Platzner M, Plessl C, Thiele L, Tröster G. Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In: Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III. Vol 4525. Proc. SPIE. ; 2001:135-146. doi:10.1117/12.434376
LibreCat
| DOI
2000 | Conference Paper | LibreCat-ID: 13609
Eisenring MH, Platzner M. An Implementation Framework for Run-time Reconfigurable Systems. In: Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE). CSREA Press; 2000:151-157.
LibreCat
2000 | Conference Paper | LibreCat-ID: 13610
Eisenring M, Platzner M. Optimization of Run-time Reconfigurable Embedded Systems. In: Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL). Springer; 2000:565-574.
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1999 | Conference Paper | LibreCat-ID: 13607
Mencer O, Platzner M. Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment. In: Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32). IEEE CS Press; 1999. doi:10.1109/hicss.1999.772883
LibreCat
| DOI
1999 | Conference Paper | LibreCat-ID: 13608
Eisenring M, Platzner M, Thiele L. Communication Synthesis for Reconfigurable Embedded Systems. In: Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL). Vol 1673. LCS. Springer; 1999:205-214. doi:10.1007/978-3-540-48302-1_21
LibreCat
| DOI
1998 | Conference Paper | LibreCat-ID: 13606
Platzner M, De Micheli G. Acceleration of satisfiability algorithms by reconfigurable hardware. In: Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) . LNCS. Berlin, Heidelberg: Springer ; 1998:69-78. doi:10.1007/bfb0055234
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| DOI
1997 | Conference Paper | LibreCat-ID: 13603
Platzner M, Peters L. Fast Signature Segmentation on a Multi-DSP Architecture. In: Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing. Vol 3166. ; 1997.
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1997 | Conference Paper | LibreCat-ID: 13604
Röwekamp T, Platzner M, Peters L. Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP. In: Proceedings of the 8th International Conference on Signal Processing Applications & Technology (ICSPAT). ; 1997:829-833.
LibreCat
1996 | Conference Paper | LibreCat-ID: 13602
Lind E, Platzner M, Rinner B. A Multi-DSP System with Dynamically Reconfigurable Processors. In: Proceedings of the 7th International Conference on Signal Processing Applications & Technology (ICSPAT). ; 1996.
LibreCat
1995 | Conference Paper | LibreCat-ID: 13469
Platzner M, Rinner B, Weiss R. A Distributed Computer Architecture for Qualitative Simulation based on a Multi-DSP and FPGAs. In: Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing . IEEE CS Press; 1995:311-318.
LibreCat
1995 | Conference Paper | LibreCat-ID: 13470
Brenner E, Ginthör-Kalcsics R, Hranitzky R, et al. High-Performance Simulators Based on Multi-TMS320C40. In: Proceedings of the 5th Annual Texas Instruments TMS320 Educators Conference. ; 1995.
LibreCat
1995 | Conference Paper | LibreCat-ID: 13471
Friedl G, Platzner M, Rinner B. A Special-Purpose Coprocessor for Qualitative Simulation. In: Proceedings of the EURO-PAR’95 International Conference on Parallel Processing. Springer International Publishing; 1995:695-698.
LibreCat
1995 | Conference Paper | LibreCat-ID: 13472
Platzner M, Rinner B, Weiss R. Parallel Qualitative Simulation. In: Proceedings of the EUROSIM Congress. Elsevier; 1995:231-236.
LibreCat
1995 | Conference Paper | LibreCat-ID: 13473
Platzner M, Rinner B. Improving Performance of the Qualitative Simulator QSIM - Design and Implementation of a Specialized Computer Architecture. In: Proceedings of the PDCS International Conference on Parallel and Distributed Computing Systems. ISCA; 1995:494-501.
LibreCat
1995 | Conference Paper | LibreCat-ID: 13474
Platzner M, Rinner B. High-Performance Qualitative Simulation on a Multi-DSP Architecture. In: Proceedings of the 6th International Conference on Signal Processing Applications & Technology (ICSPAT). ; 1995.
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1995 | Conference Paper | LibreCat-ID: 13484
Hranitzky R, Platzner M. Design and Implementation of Adaptive Digital Filters on a Multi-TMS320C40 System. In: Proceedings of the 6th International Conference on Signal Processing Applications & Technology (ICSPAT). ; 1995.
LibreCat
1994 | Conference Paper | LibreCat-ID: 13468
Platzner M, Steger C, Weiss R. Experimental Evaluation of Multi-DSP Architectures in High Performance Applications. In: Proceedings of the 7th Mediterranean Electrotechnical Conference. IEEE Press; 1994.
LibreCat
1993 | Conference Paper | LibreCat-ID: 13467
Platzner M, Steger C, Weiss R. Performance Measurements on a Multi-DSP Architecture with TMS320C40. In: Proceedings of the 4th International Conference on Signal Processing Applications & Technology (ICSPAT). DSP Associates; 1993.
LibreCat
1992 | Conference Paper | LibreCat-ID: 13465
Ginthör R, Platzner M, Weiss R. Experimental Results to Interprocessor Communication in Distributed Transputer-Systems. In: Proceedings of the 1st Austrian-Hungarian Workshop on Transputer Applications. ; 1992:45-54.
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