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226 Publications
2003 | Conference Paper | LibreCat-ID: 13615
Steiger, C., Walder, H., & Platzner, M. (2003). Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices. In Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL) (pp. 575–584). Berlin, Heidelberg: Springer. https://doi.org/10.1007/978-3-540-45234-8_56
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| DOI
2003 | Conference Paper | LibreCat-ID: 13617
Steiger, C., Walder, H., Platzner, M., & Thiele, L. (2003). Online scheduling and placement of real-time tasks to partially reconfigurable devices. In Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS) (pp. 252–235). IEEE CS Press. https://doi.org/10.1109/real.2003.1253269
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| DOI
2002 | Conference Paper | LibreCat-ID: 2423
Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., & Thiele, L. (2002). Reconfigurable Hardware in Wearable Computing Nodes. In Proc. Int. Symp. on Wearable Computers (ISWC) (pp. 215–222). IEEE Computer Society. https://doi.org/10.1109/ISWC.2002.1167250
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2002 | Conference Paper | LibreCat-ID: 2424
Dyer, M., Plessl, C., & Platzner, M. (2002). Partially Reconfigurable Cores for Xilinx Virtex. In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) (Vol. 2438, pp. 292–301). Springer. https://doi.org/10.1007/3-540-46117-5
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| DOI
2002 | Conference Paper | LibreCat-ID: 2425
Plessl, C., & Platzner, M. (2002). Custom Computing Machines for the Set Covering Problem. In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) (pp. 163–172). IEEE Computer Society. https://doi.org/10.1109/FPGA.2002.1106671
LibreCat
| DOI
2002 | Conference Paper | LibreCat-ID: 13611
Walder, H., & Platzner, M. (2002). Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform. In Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 24–30). CSREA Press.
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2001 | Conference Paper | LibreCat-ID: 2428
Plessl, C., & Platzner, M. (2001). Instance-Specific Accelerators for Minimum Covering. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 85–91). CSREA Press.
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2001 | Conference Paper | LibreCat-ID: 2432
Enzler, R., Platzner, M., Plessl, C., Thiele, L., & Tröster, G. (2001). Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III (Vol. 4525, pp. 135–146). https://doi.org/10.1117/12.434376
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| DOI
2000 | Conference Paper | LibreCat-ID: 13609
Eisenring, M. H., & Platzner, M. (2000). An Implementation Framework for Run-time Reconfigurable Systems. In Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE) (pp. 151–157). CSREA Press.
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2000 | Conference Paper | LibreCat-ID: 13610
Eisenring, M., & Platzner, M. (2000). Optimization of Run-time Reconfigurable Embedded Systems. In Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL) (pp. 565–574). Springer.
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1999 | Conference Paper | LibreCat-ID: 13607
Mencer, O., & Platzner, M. (1999). Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment. In Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32). IEEE CS Press. https://doi.org/10.1109/hicss.1999.772883
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1999 | Conference Paper | LibreCat-ID: 13608
Eisenring, M., Platzner, M., & Thiele, L. (1999). Communication Synthesis for Reconfigurable Embedded Systems. In Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL) (Vol. 1673, pp. 205–214). Springer. https://doi.org/10.1007/978-3-540-48302-1_21
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| DOI
1998 | Conference Paper | LibreCat-ID: 13606
Platzner, M., & De Micheli, G. (1998). Acceleration of satisfiability algorithms by reconfigurable hardware. In Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) (pp. 69–78). Berlin, Heidelberg: Springer . https://doi.org/10.1007/bfb0055234
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| DOI
1997 | Conference Paper | LibreCat-ID: 13603
Platzner, M., & Peters, L. (1997). Fast Signature Segmentation on a Multi-DSP Architecture. In Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing (Vol. 3166).
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1997 | Conference Paper | LibreCat-ID: 13604
Röwekamp, T., Platzner, M., & Peters, L. (1997). Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP. In Proceedings of the 8th International Conference on Signal Processing Applications & Technology (ICSPAT) (pp. 829–833).
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1996 | Conference Paper | LibreCat-ID: 13602
Lind, E., Platzner, M., & Rinner, B. (1996). A Multi-DSP System with Dynamically Reconfigurable Processors. In Proceedings of the 7th International Conference on Signal Processing Applications & Technology (ICSPAT).
LibreCat
1995 | Conference Paper | LibreCat-ID: 13469
Platzner, M., Rinner, B., & Weiss, R. (1995). A Distributed Computer Architecture for Qualitative Simulation based on a Multi-DSP and FPGAs. In Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing (pp. 311–318). IEEE CS Press.
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1995 | Conference Paper | LibreCat-ID: 13470
Brenner, E., Ginthör-Kalcsics, R., Hranitzky, R., Platzner, M., Rinner, B., Steger, C., & Weiss, R. (1995). High-Performance Simulators Based on Multi-TMS320C40. In Proceedings of the 5th Annual Texas Instruments TMS320 Educators Conference.
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1995 | Conference Paper | LibreCat-ID: 13471
Friedl, G., Platzner, M., & Rinner, B. (1995). A Special-Purpose Coprocessor for Qualitative Simulation. In Proceedings of the EURO-PAR’95 International Conference on Parallel Processing (pp. 695–698). Springer International Publishing.
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1995 | Conference Paper | LibreCat-ID: 13472
Platzner, M., Rinner, B., & Weiss, R. (1995). Parallel Qualitative Simulation. In Proceedings of the EUROSIM Congress (pp. 231–236). Elsevier.
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1995 | Conference Paper | LibreCat-ID: 13473
Platzner, M., & Rinner, B. (1995). Improving Performance of the Qualitative Simulator QSIM - Design and Implementation of a Specialized Computer Architecture. In Proceedings of the PDCS International Conference on Parallel and Distributed Computing Systems (pp. 494–501). ISCA.
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1995 | Conference Paper | LibreCat-ID: 13474
Platzner, M., & Rinner, B. (1995). High-Performance Qualitative Simulation on a Multi-DSP Architecture. In Proceedings of the 6th International Conference on Signal Processing Applications & Technology (ICSPAT).
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1995 | Conference Paper | LibreCat-ID: 13484
Hranitzky, R., & Platzner, M. (1995). Design and Implementation of Adaptive Digital Filters on a Multi-TMS320C40 System. In Proceedings of the 6th International Conference on Signal Processing Applications & Technology (ICSPAT).
LibreCat
1994 | Conference Paper | LibreCat-ID: 13468
Platzner, M., Steger, C., & Weiss, R. (1994). Experimental Evaluation of Multi-DSP Architectures in High Performance Applications. In Proceedings of the 7th Mediterranean Electrotechnical Conference. IEEE Press.
LibreCat
1993 | Conference Paper | LibreCat-ID: 13467
Platzner, M., Steger, C., & Weiss, R. (1993). Performance Measurements on a Multi-DSP Architecture with TMS320C40. In Proceedings of the 4th International Conference on Signal Processing Applications & Technology (ICSPAT). DSP Associates.
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1992 | Conference Paper | LibreCat-ID: 13465
Ginthör, R., Platzner, M., & Weiss, R. (1992). Experimental Results to Interprocessor Communication in Distributed Transputer-Systems. In Proceedings of the 1st Austrian-Hungarian Workshop on Transputer Applications (pp. 45–54).
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