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264 Publications
2024 | Conference Paper | LibreCat-ID: 45778
Luchterhandt, L., Nellius, T., Beck, R., Dömer, R., Kneuper, P., Müller, W., & Sadiye, B. (2024). Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells. MBMV 2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“. MBMV 2023 - 26. Workshop, Freiburg, , Germany, Freiburg.
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2024 | Conference Paper | LibreCat-ID: 53579
Palomero Bernardo, P., Schmid, P., Bringmann, O., Iftekhar, M., Sadiye, B., Müller, W., Koch, A., Jentsch, E., Sauer, A., Feldner, I., & Ecker, W. (2024). A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing. DATE 24 - Design Automation and Test in Europe.
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2023 | Conference Paper | LibreCat-ID: 45775
Luchterhandt, L., Nellius, T., Beck, R., Dömer, R., Kneuper, P., Müller, W., & Sadiye, B. (2023). Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture. MBMV 2023 - 26. Workshop "Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg. MBMV 2023, Freiburg, Freiburg.
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2023 | Conference Paper | LibreCat-ID: 45776
Ecker, W., Krstic, M., Ulbricht, M., Mauderer, A., Jentzsch, E., Koch, A., Koppelmann, B., Müller, W., Sadiye, B., Bruns, N., Drechsler, R., Müller-Gritschneder, D., Schlamelcher, J., Grüttner, K., Bormann, J., Kunz, W., Heckmann, R., Angst, G., Wimmer, R., … Mayr, C. (2023). Scale4Edge – Scaling RISC-V for Edge Applications. RISC-V Summit Europe 2023, Barcelona, Spain, June 2023. RISC-V Summit Europe 2023, Barcelona, Spain, June 2023., Barcelona, Spain,.
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2023 | Conference Paper | LibreCat-ID: 48530
Müller, W., Ulbricht, M., Li, L., & Krstic, M. (2023). Der TETRISC SoC - Ein resilientes Quad-Core System auf Pulpissimo-Basis. 5. ITG / GMM / GI -Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen . 5. ITG / GMM / GI -Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen , Erfurt. Germany.
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2023 | Conference Abstract | LibreCat-ID: 48961
Iftekhar, M., Gowda, H., Kneuper, P., Sadiye, B., Müller, W., & Scheytt, C. (2023). A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology. 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS). 2023 IEEE BiCMOS und Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), Monterey, CA, USA. https://doi.org/10.1109/BCICTS54660.2023.10310954
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2022 | Conference Paper | LibreCat-ID: 29302
Ecker, W., Adelt, P., Müller, W., Heckmann, R., Krstic, M., Herdt, V., Drechsler, R., Angst, G., Wimmer, R., Mauderer, A., Stahl, R., Emrich, K., Mueller-Gritschneder, D., Becker, B., Scholl, P., Jentzsch, E., Schlamelcher, J., Grüttner, K., Bernardo, P. P., … Kunz, W. (2022). The Scale4Edge RISC-V Ecosystem. In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022).
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2021 | Conference Paper | LibreCat-ID: 32125
Adelt, P., Koppelmann, B., Müller, W., & Scheytt, C. (2021). Register and Instruction Coverage Analysis for Different RISC-V ISA Modules. MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop.
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2021 | Conference Paper | LibreCat-ID: 32132
Adelt, P., Koppelmann, B., Müller, W., & Scheytt, C. (2021). QEMU zur Simulation von Worst-Case-Ausführungszeiten. MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop.
LibreCat
2021 | Conference Paper | LibreCat-ID: 23992
Adelt, P., Koppelmann, B., Müller, W., & Scheytt, C. (2021). Register and Instruction Coverage Analysis for Different RISC-V ISA Modules. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021).
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