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427 Publications
2011 | Conference Paper | LibreCat-ID: 2198
Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.” Proc. Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, 2011, pp. 278–85, doi:10.1109/IPDPS.2011.153.
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| DOI
2010 | Journal Article | LibreCat-ID: 10605
Drzevitzky, Stephanie, et al. “Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification.” International Journal of Reconfigurable Computing, vol. 2010, Hindawi Publishing Corporation, 2010, doi:10.1155/2010/180242.
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| DOI
2010 | Mastersthesis | LibreCat-ID: 10614
Agne, Andreas. Virtuelle Speicherverwaltung Für Hardware Threads in Rekonfigurierbaren Systemen. Paderborn University, 2010.
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2010 | Mastersthesis | LibreCat-ID: 10629
Boschmann, Alexander. EMG-Basierte Ganganalyse. Paderborn University, 2010.
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2010 | Mastersthesis | LibreCat-ID: 10642
Breitlauch, Daniel. Evolvable Cache Controller. Paderborn University, 2010.
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2010 | Bachelorsthesis | LibreCat-ID: 10649
Dridger, Denis. Soft Microprocessors with Tightly Coupled Application-Specific Coprocessors. Paderborn University, 2010.
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2010 | Bachelorsthesis | LibreCat-ID: 10657
Graf, Tobias. Parallelization of the UCT Algorithm on HPC-Clusters. Paderborn University, 2010.
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2010 | Conference Paper | LibreCat-ID: 10683
Kaufmann, Paul, et al. “Fluctuating EMG Signals: Investigating Long-Term Effects of Pattern Matching Algorithms.” International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), IEEE, 2010, pp. 6357–60.
LibreCat
2010 | Conference Paper | LibreCat-ID: 10686
Kaufmann, Paul, et al. “A Novel Hybrid Evolutionary Strategy and Its Periodization with Multi-Objective Genetic Optimizers.” IEEE World Congress on Computational Intelligence (WCCI), Congress on Evolutionary Computation (CEC), IEEE, 2010, pp. 541–48.
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2010 | Journal Article | LibreCat-ID: 10694
Kebschull, Udo, et al. “Selected Papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (Editorial).” IET Computers Digital Techniques, vol. 4, no. 3, 2010, pp. 157–58, doi:10.1049/iet-cdt.2010.9044.
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| DOI
2010 | Mastersthesis | LibreCat-ID: 10697
Knieper, Tobias. Hybridization of Global Multi-Objective and Local Search Techniques. Paderborn University, 2010.
LibreCat
2010 | Conference Paper | LibreCat-ID: 10699
Knieper, Tobias, et al. “Coping with Resource Fluctuations: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture.” IEEE Intl. Conf. on Evolvable Systems (ICES), vol. 6274, Springer, 2010, pp. 250–61.
LibreCat
2010 | Book Chapter | LibreCat-ID: 10704
Lübbers, Enno, and Marco Platzner. “ReconOS: An Operating System for Dynamically Reconfigurable Hardware.” Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications, edited by Marco Platzner et al., Springer-Verlag GmbH, 2010, pp. 269–90, doi:10.1007/978-90-481-3485-4_13.
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| DOI
2010 | Mastersthesis | LibreCat-ID: 10710
Meiche, Robert. FPGA/CPU Multicore-Plattform Für ReconOS/ECos. Paderborn University, 2010.
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2010 | Mastersthesis | LibreCat-ID: 10717
Niekamp, Manuel. Transparente Hardwarebeschleunigung Durch Shared Library Interposing. Paderborn University, 2010.
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2010 | Mastersthesis | LibreCat-ID: 10731
Runde, Bodo. A Token-Ring Network-On-Chip for Message Passing in ReconOS. Paderborn University, 2010.
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2010 | Mastersthesis | LibreCat-ID: 10752
Wiersema, Tobias. Scheduling Support for Heterogeneous Hardware Accelerators under Linux. Paderborn University, 2010.
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2010 | Book (Editor) | LibreCat-ID: 10763
Platzner, Marco, et al., editors. Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications. Springer-Verlag GmbH, 2010, doi:10.1007/978-90-481-3485-4.
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| DOI
2010 | Conference Paper | LibreCat-ID: 10776
Khatir, Mehrdad, et al. “Sub-Threshold Charge Recovery Circuits.” Computer Design (ICCD), 2010 IEEE International Conference On, IEEE, 2010, pp. 138–44, doi:10.1109/ICCD.2010.5647815.
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| DOI
2010 | Conference Paper | LibreCat-ID: 13640
Giefers, Heiner, and Marco Platzner. “A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier.” Proceedings of the 20th International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2010.
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