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450 Publications
2012 | Journal Article | LibreCat-ID: 2174
Kasap S, Benkrid K. Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer. Journal of Computers. 2012;7(6):1312-1328.
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2012 | Dissertation | LibreCat-ID: 586 | 
Drzevitzky S. Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn; 2012.
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2012 | Misc | LibreCat-ID: 587
Plessl C, Platzner M, Agne A, Happe M, Lübbers E. Programming Models for Reconfigurable Heterogeneous Multi-Cores. Awareness Magazine; 2012.
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2012 | Conference Paper | LibreCat-ID: 10636
Boschmann A, Platzner M. Reducing classification accuracy degradation of pattern recognition based myoelectric control caused by electrode shift using a high density electrode array. In: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC). ; 2012.
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2012 | Mastersthesis | LibreCat-ID: 10650
Dridger D. Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer. Paderborn University; 2012.
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2012 | Dissertation | LibreCat-ID: 10652
Giefers H. Design and Programming of Reconfigurable Mesh Based Many-Cores. Berlin: Logos Verlag Berlin GmbH; 2012.
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2012 | Mastersthesis | LibreCat-ID: 10658
Graf T. Adaptive Playouts in Der Monte-Carlo Spielbaumsuche Am Anwendungsfall Go. Paderborn University; 2012.
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2012 | Bachelorsthesis | LibreCat-ID: 10667
Hangmann H. Generating Adjustable Temperature Gradients on Modern FPGAs. Paderborn University; 2012.
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2012 | Journal Article | LibreCat-ID: 10685
Kaufmann P, Glette K, Platzner M, Torresen J. Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture. International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS). 2012;3(4):17-31. doi:10.4018/jaras.2012100102
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| DOI
2012 | Misc | LibreCat-ID: 10723
Platzner M, Boschmann A, Kaufmann P. Wieder Natürlich Gehen Und Greifen.; 2012:6-11.
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2012 | Bachelorsthesis | LibreCat-ID: 10734
Schmitz H. Stereo Matching on a HC-1 Hybrid Core Computer. Paderborn University; 2012.
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2012 | Bachelorsthesis | LibreCat-ID: 10747
Topmöller C. Entwicklung Eines Picoblaze Compilers Mit Dem Gentle Compiler Construction System. Paderborn University; 2012.
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2012 | Mastersthesis | LibreCat-ID: 10754
Wistuba M. Analysis of Pattern Based Model Design and Learning in Computer-Go. Paderborn University; 2012.
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2012 | Misc | LibreCat-ID: 13462
Lewis P, Platzner M, Yao X. An Outlook for Self-Awareness in Computing Systems. Awareness Magazine; 2012.
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2012 | Conference Paper | LibreCat-ID: 2106
Meyer B, Schumacher J, Plessl C, Förstner J. Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2012:189-196. doi:10.1109/FPL.2012.6339370
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2012 | Journal Article | LibreCat-ID: 2108
Schumacher T, Plessl C, Platzner M. IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. Microprocessors and Microsystems. 2012;36(2):110-126. doi:10.1016/j.micpro.2011.04.002
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2012 | Conference Paper | LibreCat-ID: 615
Happe M, Hangmann H, Agne A, Plessl C. Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. In: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416745
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2012 | Conference Paper | LibreCat-ID: 591
Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware efficiency for ease of use? In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416773
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2012 | Conference Paper | LibreCat-ID: 609
Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware Compute Nodes. In: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS). ; 2012:8-9.
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2012 | Conference Paper | LibreCat-ID: 567
Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs into function calls: Code generation for heterogeneous architectures. In: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS). IEEE; 2012:559-565. doi:10.1109/HPCSim.2012.6266973
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