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427 Publications
2010 | Conference Paper | LibreCat-ID: 13641
Schäfer, Wilhelm, et al. “Engineering Self-Coordinating Software Intensive Systems.” Proceedings of the Foundations of Software Engineering (FSE) and NITR & D/SPD Working Conference on the Future of Software Engineering Research (FoSER), 2010, pp. 321–24.
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2010 | Conference Paper | LibreCat-ID: 13642
Giefers, Heiner, and Marco Platzner. “A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics.” Proceedings of the 10th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010.
LibreCat
2010 | Conference Paper | LibreCat-ID: 2223
Lübbers, Enno, et al. “Towards Adaptive Networking for Embedded Devices Based on Reconfigurable Hardware.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 225–31.
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2010 | Conference Paper | LibreCat-ID: 2216
Grad, Mariusz, and Christian Plessl. “Pruning the Design Space for Just-In-Time Processor Customization.” Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, 2010, pp. 67–72, doi:10.1109/ReConFig.2010.19.
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| DOI
2010 | Conference Paper | LibreCat-ID: 2224
Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with Benchmarking Facilities.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 144–50.
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2010 | Conference Paper | LibreCat-ID: 2220
Andrews, David, and Christian Plessl. “Configurable Processor Architectures: History and Trends.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, p. 165.
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2010 | Conference (Editor) | LibreCat-ID: 2222
Plaks, Toomas P., et al., editors. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press, 2010.
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2010 | Conference Paper | LibreCat-ID: 2226
Beisel, Tobias, et al. “Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators.” Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010, pp. 65–72, doi:10.1109/ASAP.2010.5540798.
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| DOI
2010 | Conference Paper | LibreCat-ID: 2206
Keller, Ariane, et al. “Reconfigurable Nodes for Future Networks.” Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp. 372–76, doi:10.1109/GLOCOMW.2010.5700341.
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| DOI
2010 | Conference Paper | LibreCat-ID: 2228
Kenter, Tobias, et al. “Performance Estimation for the Exploration of CPU-Accelerator Architectures.” Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), edited by Omar Hammami and Sandra Larrabee, 2010.
LibreCat
2009 | Conference Paper | LibreCat-ID: 10639
Boschmann, Alexander, et al. “Towards Multi-Movement Hand Prostheses: Combining Adaptive Classification with High Precision Sockets.” Proc. Technically Assisted Rehabilitation (TAR), 2009.
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2009 | Mastersthesis | LibreCat-ID: 10702
Kostin, Alexander. Evolvable Robot Controller. Paderborn University, 2009.
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2009 | Journal Article | LibreCat-ID: 10703
Lübbers, Enno, and Marco Platzner. “ReconOS: Multithreaded Programming for Reconfigurable Computers.” ACM Transactions on Embedded Computing Systems, vol. 9, no. 1, 2009, pp. 8:1-8:33, doi:10.1145/1596532.1596540.
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| DOI
2009 | Mastersthesis | LibreCat-ID: 10746
Tofall, Martin. Compiler for a Custom Instruction Set CPU. Paderborn University, 2009.
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2009 | Mastersthesis | LibreCat-ID: 10749
Warkentin, Alexander. Coarse-Grained CGP Model Using Xilinx Virtex5 DSP48E Functional Units. Paderborn University, 2009.
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2009 | Bachelorsthesis | LibreCat-ID: 10753
Wildenhain, Benedikt. Implementierung von Kryptographie-Hardwarebeschleunigern Für Das HW/SW-Betriebssystem ReconOS. Paderborn University, 2009.
LibreCat
2009 | Conference Paper | LibreCat-ID: 10777
Ghasemzadeh Mohammadi, Hassan, et al. “Signature Self Checking (SSC): A Low-Cost Reliable Control Logic for Pipelined Microprocessors.” Dependable Computing (PRDC), 2009 IEEE Pacific Rim International Symposium On, IEEE, 2009, pp. 252–55, doi:10.1109/PRDC.2009.69.
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| DOI
2009 | Conference Paper | LibreCat-ID: 13632
Happe, Markus, et al. “A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms.” Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC), Springer, 2009.
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2009 | Conference Paper | LibreCat-ID: 13634
Giefers, Heiner, and Marco Platzner. “Towards Models for Many-Cores: The Case for the Reconfigurable Mesh.” Proceedings of the Workshop on Many-Cores, International Conference on Architecture of Computing Systems (ARCS), 2009.
LibreCat
2009 | Conference Paper | LibreCat-ID: 13635
Giefers, Heiner, and Marco Platzner. “ARMLang: A Language and Compiler for Programming Reconfigurable Mesh Many-Cores.” Reconfigurable Architectures Workshop (RAW), Proceedings of the International Parallel and Distributed Processing Symposium, IEEE, 2009.
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