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7 Publications
2017 | Conference Paper | LibreCat-ID: 10676
Ho N, Kaufmann P, Platzner M. Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In: 2017 International Conference on Field Programmable Technology (ICFPT). ; 2017:215-218. doi:10.1109/FPT.2017.8280144
LibreCat
| DOI
2017 | Conference Paper | LibreCat-ID: 48856
Bossek J, Grimme C. An Extended Mutation-Based Priority-Rule Integration Concept for Multi-Objective Machine Scheduling. In: 2017 IEEE Symposium Series on Computational Intelligence (SSCI). ; 2017:1–8. doi:10.1109/SSCI.2017.8285224
LibreCat
| DOI
2015 | Conference Paper | LibreCat-ID: 10673
Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS). ; 2015:1-7. doi:10.1109/AHS.2015.7231178
LibreCat
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2014 | Conference Paper | LibreCat-ID: 10677
Ho N, Kaufmann P, Platzner M. Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. In: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES). ; 2014:31-37. doi:10.1109/ICES.2014.7008719
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2013 | Conference Paper | LibreCat-ID: 36920
He D, Müller W. An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors. In: Weghorn H, ed. Proceedings of the International Conference on Applied Computing (AC). ; 2013.
LibreCat
2010 | Conference Paper | LibreCat-ID: 37009
Oliveira MFS, Zabel H, Müller W. Assertion-Based Verification of RTOS Properties. In: Proceedings of DATE’10. IEEE; 2010. doi:10.1109/DATE.2010.5457130
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1996 | Conference Paper | LibreCat-ID: 39526
Geiger C, Hunstock R, Lehrenfeld G, et al. Visual Modeling and 3D-Representation with a Complete Visual Programming Language --- A Case Study in Manufacturing. In: Proceedings of the 1996 IEEE Symposium on Visual Languages. ; 1996. doi:10.1109/VL.1996.545302
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