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29 Publications


2022 | Dissertation | LibreCat-ID: 29769 | OA
Hardware Trojans in Reconfigurable Computing
Q.A. Ahmed, Hardware Trojans in Reconfigurable Computing, Paderborn University, Paderborn, Germany, Paderborn, 2022.
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2021 | Dissertation | LibreCat-ID: 26746 | OA
Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware
T. Wiersema, Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware, Paderborn University, Paderborn, 2021.
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2021 | Mastersthesis | LibreCat-ID: 29151
A Comparison of Machine Learning Techniques for the On-line Characterization of Tasks Executed on Heterogeneous Compute Nodes
C. Kashikar, A Comparison of Machine Learning Techniques for the On-Line Characterization of Tasks Executed on Heterogeneous Compute Nodes, Paderborn University, Paderborn, 2021.
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2021 | Bachelorsthesis | LibreCat-ID: 22216
Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib
J.W. Rehnen, Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib, 2021.
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2021 | Bachelorsthesis | LibreCat-ID: 22483
Implementation and Profiling of XCS in the Context of Embedded Systems
M. Brede, Implementation and Profiling of XCS in the Context of Embedded Systems, Paderborn University, Paderborn, 2021.
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2021 | Mastersthesis | LibreCat-ID: 29540
Design and Implementation of a ReconROS-based Obstacle Avoidance System
M.A. Sheikh, Design and Implementation of a ReconROS-Based Obstacle Avoidance System, Paderborn University, 2021.
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2020 | Mastersthesis | LibreCat-ID: 21324
Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis
K. Chandrakar, Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis, 2020.
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2020 | Bachelorsthesis | LibreCat-ID: 21432
Evaluation of a ReconOS-ROS Combination based on a Video Processing Application
L.-S. Henke, Evaluation of a ReconOS-ROS Combination Based on a Video Processing Application, 2020.
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2020 | Mastersthesis | LibreCat-ID: 21433
Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture
F.P. Jentzsch, Design and Implementation of a ReconOS-Based TensorFlow Lite Delegate Architecture, 2020.
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2020 | Bachelorsthesis | LibreCat-ID: 20820
Implementing Machine Learning Functions as PYNQ FPGA Overlays
S. Thiele, Implementing Machine Learning Functions as PYNQ FPGA Overlays, 2020.
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2020 | Mastersthesis | LibreCat-ID: 20821
Extension and Evaluation of Python-based High-Level Synthesis Tool Flows
V. Jaganath, Extension and Evaluation of Python-Based High-Level Synthesis Tool Flows, 2020.
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2019 | Mastersthesis | LibreCat-ID: 15874 | OA
Implementing a Real-time System on a Platform FPGA operated with ReconOS
C. Lienen, Implementing a Real-Time System on a Platform FPGA Operated with ReconOS, Universität Paderborn, n.d.
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2019 | Mastersthesis | LibreCat-ID: 15920
A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking
M. Keerthipati, A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking, Universität Paderborn, 2019.
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2019 | Mastersthesis | LibreCat-ID: 14831
FPGA Acceleration of String Search Techniques in Huge Data Sets
N.S. Sabu, FPGA Acceleration of String Search Techniques in Huge Data Sets, Paderborn University, 2019.
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2019 | Mastersthesis | LibreCat-ID: 14546
Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers
T. Hansmeier, Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers, Universität Paderborn, 2019.
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2018 | Bachelorsthesis | LibreCat-ID: 3365
Static Scheduling Algorithms for Heterogeneous Compute Nodes
J.-P. Schnuer, Static Scheduling Algorithms for Heterogeneous Compute Nodes, Universität Paderborn, 2018.
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2018 | Bachelorsthesis | LibreCat-ID: 3366
Evaluation of OpenCL-based Compilation for FPGAs
M. Croce, Evaluation of OpenCL-Based Compilation for FPGAs, Universität Paderborn, 2018.
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2018 | Dissertation | LibreCat-ID: 3720
FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization
N. Ho, FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization, Universität Paderborn, 2018.
LibreCat | DOI
 

2017 | Bachelorsthesis | LibreCat-ID: 3580
An FPGA Accelerator for Checking Resolution Proofs
T. Hansmeier, An FPGA Accelerator for Checking Resolution Proofs, Universität Paderborn, 2017.
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2017 | Mastersthesis | LibreCat-ID: 1157
A Framework for the Synthesis of Approximate Circuits
L.M. Witschen, A Framework for the Synthesis of Approximate Circuits, Universität Paderborn, 2017.
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