Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime

J. Anwer, S. Meisner, M. Platzner, in: Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On, 2013, pp. 1–6.

Download
No fulltext has been uploaded.
Conference Paper | English
Author
Anwer, Jahanzeb; Meisner, Sebastian; Platzner, MarcoLibreCat
Publishing Year
Proceedings Title
Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on
Page
1-6
LibreCat-ID

Cite this

Anwer J, Meisner S, Platzner M. Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime. In: Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On. ; 2013:1-6. doi:10.1109/ReConFig.2013.6732280
Anwer, J., Meisner, S., & Platzner, M. (2013). Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime. In Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on (pp. 1–6). https://doi.org/10.1109/ReConFig.2013.6732280
@inproceedings{Anwer_Meisner_Platzner_2013, title={Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime}, DOI={10.1109/ReConFig.2013.6732280}, booktitle={Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on}, author={Anwer, Jahanzeb and Meisner, Sebastian and Platzner, Marco}, year={2013}, pages={1–6} }
Anwer, Jahanzeb, Sebastian Meisner, and Marco Platzner. “Dynamic Reliability Management: Reconfiguring Reliability-Levels of Hardware Designs at Runtime.” In Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On, 1–6, 2013. https://doi.org/10.1109/ReConFig.2013.6732280.
J. Anwer, S. Meisner, and M. Platzner, “Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime,” in Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on, 2013, pp. 1–6.
Anwer, Jahanzeb, et al. “Dynamic Reliability Management: Reconfiguring Reliability-Levels of Hardware Designs at Runtime.” Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On, 2013, pp. 1–6, doi:10.1109/ReConFig.2013.6732280.

Export

Marked Publications

Open Data LibreCat

Search this title in

Google Scholar