Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study

P.-E. Gaillardon, H. Ghasemzadeh Mohammadi, G. De Micheli, in: 2013 14th Latin American Test Workshop-LATW, IEEE, 2013, pp. 1–6.

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2013 14th Latin American Test Workshop-LATW
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Gaillardon P-E, Ghasemzadeh Mohammadi H, De Micheli G. Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study. In: 2013 14th Latin American Test Workshop-LATW. IEEE; 2013:1-6. doi:10.1109/LATW.2013.6562673
Gaillardon, P.-E., Ghasemzadeh Mohammadi, H., & De Micheli, G. (2013). Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study. In 2013 14th Latin American Test Workshop-LATW (pp. 1–6). IEEE. https://doi.org/10.1109/LATW.2013.6562673
@inproceedings{Gaillardon_Ghasemzadeh Mohammadi_De Micheli_2013, title={Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study}, DOI={10.1109/LATW.2013.6562673}, booktitle={2013 14th Latin American Test Workshop-LATW}, publisher={IEEE}, author={Gaillardon, Pierre-Emmanuel and Ghasemzadeh Mohammadi, Hassan and De Micheli, Giovanni}, year={2013}, pages={1–6} }
Gaillardon, Pierre-Emmanuel, Hassan Ghasemzadeh Mohammadi, and Giovanni De Micheli. “Vertically-Stacked Silicon Nanowire Transistors with Controllable Polarity: A Robustness Study.” In 2013 14th Latin American Test Workshop-LATW, 1–6. IEEE, 2013. https://doi.org/10.1109/LATW.2013.6562673.
P.-E. Gaillardon, H. Ghasemzadeh Mohammadi, and G. De Micheli, “Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study,” in 2013 14th Latin American Test Workshop-LATW, 2013, pp. 1–6.
Gaillardon, Pierre-Emmanuel, et al. “Vertically-Stacked Silicon Nanowire Transistors with Controllable Polarity: A Robustness Study.” 2013 14th Latin American Test Workshop-LATW, IEEE, 2013, pp. 1–6, doi:10.1109/LATW.2013.6562673.

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