Multiobjective optimization for transistor sizing of CMOS logic standard cells using set-oriented numerical techniques

M. Blesken, U. Ruckert, D. Steenken, K. Witting, M. Dellnitz, in: 2009 NORCHIP, 2009.

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2009 NORCHIP
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Blesken M, Ruckert U, Steenken D, Witting K, Dellnitz M. Multiobjective optimization for transistor sizing of CMOS logic standard cells using set-oriented numerical techniques. In: 2009 NORCHIP. ; 2009. doi:10.1109/norchp.2009.5397800
Blesken, M., Ruckert, U., Steenken, D., Witting, K., & Dellnitz, M. (2009). Multiobjective optimization for transistor sizing of CMOS logic standard cells using set-oriented numerical techniques. In 2009 NORCHIP. https://doi.org/10.1109/norchp.2009.5397800
@inproceedings{Blesken_Ruckert_Steenken_Witting_Dellnitz_2009, title={Multiobjective optimization for transistor sizing of CMOS logic standard cells using set-oriented numerical techniques}, DOI={10.1109/norchp.2009.5397800}, booktitle={2009 NORCHIP}, author={Blesken, Matthias and Ruckert, Ulrich and Steenken, Dominik and Witting, Katrin and Dellnitz, Michael}, year={2009} }
Blesken, Matthias, Ulrich Ruckert, Dominik Steenken, Katrin Witting, and Michael Dellnitz. “Multiobjective Optimization for Transistor Sizing of CMOS Logic Standard Cells Using Set-Oriented Numerical Techniques.” In 2009 NORCHIP, 2009. https://doi.org/10.1109/norchp.2009.5397800.
M. Blesken, U. Ruckert, D. Steenken, K. Witting, and M. Dellnitz, “Multiobjective optimization for transistor sizing of CMOS logic standard cells using set-oriented numerical techniques,” in 2009 NORCHIP, 2009.
Blesken, Matthias, et al. “Multiobjective Optimization for Transistor Sizing of CMOS Logic Standard Cells Using Set-Oriented Numerical Techniques.” 2009 NORCHIP, 2009, doi:10.1109/norchp.2009.5397800.

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