Verification Closure of SystemC Designs with Functional Coverage

In the area of dynamic verification of virtual prototypes, functional coverage is a valuable tool for answering the "Are we done?" question and achieving verification closure. Recent verification methodologies such as OVM and UVM contain multi-language support that provides a basic SystemC version. However, due to language shortcoming they cannot be utilized for the same amount of verification tasks in the SystemC ecosystem as in other supported hardware design and verification languages. In this presentation, we propose to boost the verification capabilities of SystemC by implementing functional coverage collection and evaluation according to the same metric as defined in the widely accepted IEEE-1800 SystemVerilog cover group feature. We implement a functional coverage library to enable coverage-driven verification of SystemC designs on multiple levels of abstraction enabling value, transition, and expression coverage. To our knowledge, the overall functionalities are not available in the IEEE-1666 SystemC standard or the SCV add-on library, nor are they complete compared to the aforementioned in any publicly available SystemC library.