72 Publications

Mark all

[72]
2021 | Conference Paper | LibreCat-ID: 23992
Register and Instruction Coverage Analysis for Different RISC-V ISA Modules
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021), 2021.
LibreCat
 
[71]
2020 | Conference Paper | LibreCat-ID: 24027
A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, Stuttgart, DE, 2020.
LibreCat | Files available
 
[70]
2019 | Conference Paper | LibreCat-ID: 24058
RISC-V Extensions for Bit Manipulation Instructions
B. Koppelmann, P. Adelt, W. Müller, C. Scheytt, in: 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Rhodos, Griechenland, 2019.
LibreCat | Files available | DOI
 
[69]
2019 | Conference Paper | LibreCat-ID: 24060
Analyse sicherheitskritischer Software für RISC-V Prozessoren
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019), Kaiserslautern, DE, 2019.
LibreCat | Files available
 
[68]
2019 | Conference Paper | LibreCat-ID: 24061
QEMU for Dynamic Memory Analysis of Security Sensitive Software
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, B. Driessen, in: 2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019, Florence, Italy, 2019, pp. 32–34.
LibreCat | Files available
 
[67]
2019 | Journal Article | LibreCat-ID: 24063
QEMU Support for RISC-V: Current State and Future Releases
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, 2nd International Workshop on RISC-V Research Activities (Presentation) (2019).
LibreCat | Files available
 
[66]
2018 | Journal Article | LibreCat-ID: 24194
Current and Future RISC-V Activities for Virtual Prototyping and Chip Design
P. Adelt, B. Koppelmann, W. Müller, International Workshop on RISC-V Research Activities Presentation (2018).
LibreCat | Files available
 
[65]
2018 | Conference Paper | LibreCat-ID: 24196
Analog fault simulation automation at schematic level with random sampling techniques
L. Wu, M.K. Hussain, S. Abughannam, W. Müller, C. Scheytt, W. Ecker, in: 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)) , IEEE, Italy/Taormina, 2018.
LibreCat | Files available | DOI
 
[64]
2017 | Conference Paper | LibreCat-ID: 24224
ANALISA - A Tool for Static Instruction Set Analysis
P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, C. Scheytt, in: Design Automation and Testing in Europe (DATE), University Booth Interactive Presentation, Lausanne, CH, 2017.
LibreCat | Files available
 
[63]
2017 | Conference Paper | LibreCat-ID: 25069
ANALISA - A Tool for Static Instruction Set Analysis
P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, J.C. Scheytt, in: University Booth Interactive Presentation (Ed.), Design Automation and Testing in Europe (DATE), 2017.
LibreCat
 
[62]
2017 | Conference Paper | LibreCat-ID: 24225
An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries
P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, C. Scheytt, in: 2nd Workshop on Resiliency in Embedded Electronic Systems (REES) , Lausanne, Switzerland, 2017, p. 44.
LibreCat | Files available
 
[61]
2017 | Conference Paper | LibreCat-ID: 24220
Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen
P. Adelt, B. Koppelmann, W. Müller, D. Mueller-Gritschneder, B. Kleinjohann, C. Scheytt, in: Tagungsband des Wissenschaftsforums Intelligente Technische Systeme, Verlagsschriftenreihe des Heinz Nixdorf Instituts, Germany, Paderborn, 2017.
LibreCat | Files available | DOI
 
[60]
2017 | Conference Paper | LibreCat-ID: 24223
SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study
L. Wu, S. Abughannam, W. Müller, C. Scheytt, W. Ecker, in: 2nd Workshop on Resiliency in Embedded Electronic Systems (REES), Lausanne, Switzerland, 2017, p. 68.
LibreCat | Files available
 
[59]
2016 | Conference Paper | LibreCat-ID: 24263
Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study
S. Abughannam, L. Wu, W. Müller, C. Scheytt, in: Analog 2016 - VDE, 2016.
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[58]
2016 | Conference Paper | LibreCat-ID: 24264
Fast Dynamic Fault Injection for Virtual Microcontroller Platforms
P. Adelt, B. Koppelmann, W. Müller, M. Becker, B. Kleinjohann, C. Scheytt, in: Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC), Tallin, Estonia, 2016.
LibreCat | DOI
 
[57]
2015 | Conference Paper | LibreCat-ID: 24289
On the Correlation of HW Faults and SW Errors
W. Müller, L. Wu, C. Scheytt, M. Becker, S. Schoenberg, in: D. Mueller-Gritschneder, W. Müller, S. Mitra (Eds.), Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014), Amsterdam, Netherland, 2015.
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[56]
2014 | Conference Paper | LibreCat-ID: 25145
Virtual Platforms for Model-Based Design of Dependable Cyber-Physical System Software
M. Becker, C. Kuznik, W. Müller, in: 17th Euromicro Conference on Digital Systems Design (DSD), 2014.
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[55]
2014 | Journal Article | LibreCat-ID: 25164
HeroeS³ -- A Framework for Heterogeneous Software-Intensive System Design with SystemC
M. Becker, W. Müller, J. Stroop, U. Kiffmeier, Design, Automation and Test in Europe DATE, University Booth, Dresden (2014).
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[54]
2014 | Conference Paper | LibreCat-ID: 25169
Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges
J.-H. Oetjens, M. Becker, C. Kuznik, W. Müller, in: Design Automation Conference (DAC), 2014.
LibreCat
 
[53]
2014 | Journal Article | LibreCat-ID: 24302
Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU
B. Koppelmann, B. Messidat, M. Becker, C. Kuznik, W. Müller, C. Scheytt, Design and Verification Conference (DVCON EUROPE) (2014).
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[52]
2014 | Conference Paper | LibreCat-ID: 25146
Source code annotated memory leak detection for soft real time embedded systems with resource constraints
M. tech. M.M. Joy, W. Müller, F.-J. Rammig, in: 12th IEEE International Conference on Embedded Computing, 2014.
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[51]
2014 | Conference Paper | LibreCat-ID: 25161
Portierung der TriCore-Architektur auf QEMU
B. Koppelmann, M. Becker, W. Müller, in: 17. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2014) , 2014.
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[50]
2014 | Conference Paper | LibreCat-ID: 25166
Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM
C. Kuznik, W. Müller, in: 26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, 2014.
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[49]
2014 | Journal Article | LibreCat-ID: 24309
Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure
C. Kuznik, W. Müller, Design, Automation and Test in Europe DATE, University Booth, Dresden (2014).
LibreCat
 
[48]
2014 | Conference Paper | LibreCat-ID: 24311
Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges
J.-H. Oetjens, M. Becker, C. Kuznik, W. Müller, in: Design Automation Conference (DAC), 2014.
LibreCat | DOI
 
[47]
2014 | Journal Article | LibreCat-ID: 25117
Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU
B. Koppelmann, B. Messidat, M. Becker, C. Kuznik, W. Müller, J.C. Scheytt, Design and Verification Conference (DVCON EUROPE) (2014).
LibreCat
 
[46]
2014 | Conference Paper | LibreCat-ID: 25155
Fault Effect Modeling in a Heterogeneous SystemC Virtual Platform Framework for Cyber-Physical Systems
M. Becker, C. Kuznik, W. Müller, in: ACM/IEEE 5th International Conference on Cyber-Physical Systems, 2014.
LibreCat
 
[45]
2014 | Journal Article | LibreCat-ID: 25162
Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure
C. Kuznik, W. Müller, Design, Automation and Test in Europe DATE, University Booth, Dresden (2014).
LibreCat
 
[44]
2014 | Conference Paper | LibreCat-ID: 24305
Architectural Low-Power Design Using Transaction-Based System Modeling and Simulation
F. Mischkalla, W. Müller, in: Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), IEEE, Greece, 2014.
LibreCat | DOI
 
[43]
2014 | Conference Paper | LibreCat-ID: 25120
Architectural Low-Power Design Using Transaction-Based System Simulation
F. Mischkalla, W. Müller, in: Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), IEEE, 2014.
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[42]
2014 | Conference Paper | LibreCat-ID: 25144
Advanced SoC Virtual Prototyping for System-Level Power Planning and Validation
F. Mischkalla, W. Müller, in: PATMOS 2014, Palma de Mallorca, Spain, 2014.
LibreCat
 
[41]
2014 | Journal Article | LibreCat-ID: 25151
An Assisted Single Source Verification Metric Model Code Generation Methodology
C. Kuznik, B.G. Defo, W. Müller, Electronic System Level Synthesis Conference (ESLSyn) (2014).
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[40]
2014 | Conference Paper | LibreCat-ID: 25163
Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung
C. Kuznik, B.G. Defo, W. Müller, in: 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) , 2014.
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[39]
2013 | Conference Paper | LibreCat-ID: 25284
Efficient Power Intent Validation Using Loosely-Timed Simulation Models
F. Mischkalla, W. Müller, in: 23rd International Workshop on Power And Timing Modeling, Optimization and Simulation, Sep. 2013, 2013.
LibreCat
 
[38]
2013 | Conference Paper | LibreCat-ID: 25291
HeroeS: Virtual Platform Driven Integration of Heterogeneous Software Components for Multi-Core Real-Time Architectures
M. Becker, U. Kiffmeier, W. Müller, in: 16th IEEE Computer Society Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2013.
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[37]
2013 | Conference Paper | LibreCat-ID: 25614
SC OVM: An Advanced SystemC Library for OVM-based Verification
C. Kuznik, M. F. S. Oliveira, W. Müller, in: Open SANITAS SystemC Verification Workshop, 2013.
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[36]
2013 | Newspaper Article | LibreCat-ID: 25615
Informationstechnik spart Ressourcen
G. Engels, C. Gerth, L. Kleinjohann, B. Kleinjohann, W. Müller, ForschungsForum Paderborn (2013).
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[35]
2013 | Book Chapter | LibreCat-ID: 25743
Methods for the Design and Development
H. Anacker, M. Dellnitz, K. Flaßkamp, S. Grösbrink, P. Hartmann, C. Heinzemann, C. Horenkamp, L. Kleinjohann, B. Kleinjohann, S. Korf, M. Krüger, W. Müller, S. Ober-Blöbaum, S. Oberthür, M. Porrmann, C. Priesterjahn, W. Radkowski, C. Rasche, J. Rieke, M. Ringkamp, K. Stahl, D. Steenken, J. Stöcklein, R. Timmermann, A. Trächtler, K. Witting, T. Xie, S. Ziegert, in: Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future, Springer-Verlag, Heidelberg, 2013, pp. 187–356.
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[34]
2013 | Conference Paper | LibreCat-ID: 25270
Early Phase Memory Leak Detection in Embedded Software Designs with Virtual Memory Management Model
M. tech. M.M. Joy, W. Müller, F.-J. Rammig, in: Proceedings of AVICPS 2013, Dez. 2013 IEEE Computer Society, Linköping University Electronic Press, 2013.
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[33]
2013 | Conference Paper | LibreCat-ID: 25612
Funktionale Verifikation von Low-Power Designs unter Verwendung Virtueller Prototypen
F. Mischkalla, W. Müller, in: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013.
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[32]
2013 | Conference Paper | LibreCat-ID: 25271
AN ENERGY-EFFICIENT HEURISTIC FOR HARD REAL- TIME SYSTEM ON MULTI-CORE PROCESSORS
D. He, W. Müller, in: Proceedings of International Conference on Applied Computing (AC), 2013.
LibreCat
 
[31]
2013 | Conference Paper | LibreCat-ID: 25606
SystemC Verification Components - An enhanced OVM/UVM for SystemC
C. Kuznik, M. F. S. Oliveira, W. Müller, in: EdaWorkshop 13, 2013.
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[30]
2013 | Conference Paper | LibreCat-ID: 25620
Systematic Application of UCIS to Improve the Automation on Verification Closure
C. Kuznik, M.F. Oliveira, B. Defo, W. Müller, in: Proceedings of DVCON, 2013.
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[29]
2013 | Conference Paper | LibreCat-ID: 25632
Fault-Tolerant Deployment of Real-Time Software in AUTOSAR ECU Networks
K. Klobedanz, J. Jatzkowski, A. Rettberg, W. Müller, in: International Embedded Systems Symposium (IESS) 2013, Springer, 2013.
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[28]
2013 | Journal Article | LibreCat-ID: 25740
A heuristic energy-aware approach for hard real-time systems on multi-core platforms
D. He, W. Müller, Microprocessors and Microsystems - Embedded Hardware Design 37(6-7) (2013) 845–857.
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[27]
2012 | Conference Paper | LibreCat-ID: 25758
XEMU: An Efficient QEMU Based Binary Mutation Testing Framework for Embedded Software
M. Becker, D. Baldin, C. Kuznik, M. tech. M.M. Joy, T. Xie, W. Müller, in: EMSOFT’12: Teenth ACM International Conference on Embedded Software 2012 Proceedings , 2012.
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[26]
2012 | Conference Paper | LibreCat-ID: 26023
Enhanced Schedulability Analysis of Hard Real-Time Systems on Power Manageable Multi-Core Platforms
D. He, W. Müller, in: Third International Symposium on Advances in Embedded Systems and Applications (ESA-2012), IEEE Xplore, 2012.
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[25]
2012 | Conference Paper | LibreCat-ID: 26080
XEMU: A QEMU Based Binary Mutation Testing Framework
M. Becker, C. Kuznik, M. tech. M. Joy, T. Xie, W. Müller, in: Design, Automation and Test in Europe DATE, University Booth, Dresden, 2012.
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[24]
2012 | Conference Paper | LibreCat-ID: 26092
Virtual Prototyping of Cyber-Physical Systems
W. Müller, M. Becker, H. Zabel, A. Elfeky, A. DiPasquale, in: In Proceedings of 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012, Sydney, 2012.
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[23]
2012 | Conference Paper | LibreCat-ID: 25761
The System Verification Methodology for Advanced TLM Verification
M.F. Oliveira, C. Kuznik, H.M. Le, D. Große, F. Haedicke, W. Müller, R. Drechsler, W. Ecker, V. Esen, in: CODES/ISSS ’12: Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Proceedings, 2012.
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[22]
2012 | Conference Paper | LibreCat-ID: 26024
Compilation of Methodologies to Speed up the Verification Process at System Level
S. Radke, S. Rülke, M.F. Oliveira, C. Kuznik, W. Müller, W. Ecker, V. Esen, S. Hufnagel, N. Bannow, J.-H. Oetjens, H. Brazdrum, P. Janssen, H.M. Le, D. Große, F. Haedicke, R. Drechsler, G. Koch, A. Burger, O. Bringmann, W. Rosenstiel, R. Görgen, in: EdaWorkshop 12, 2012.
LibreCat | Download (ext.)
 
[21]
2012 | Conference Paper | LibreCat-ID: 26031
Online Energy-Efficient Hard Real-Time Scheduling for Component Oriented Systems
D. He, W. Müller, in: 2012 IEEE 15th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC), IEEE Xplore, 2012.
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[20]
2012 | Conference Paper | LibreCat-ID: 26036
A SystemC Library for Advanced TLM Verification
M.F. Oliveira, C. Kuznik, W. Müller, W. Ecker, V. Esen, in: Proceeding of Design and Verification Conference (DVCON), 2012.
LibreCat
 
[19]
2012 | Conference Paper | LibreCat-ID: 26079
MOUSSE: scaling MOdelling and verification to complex heterogeneoUS embedded Systems Evolution
M. Becker, G.B. Gnokam Defo, W. Müller, F. Fummi, G. Pravadelli, S. Vinco, in: Design, Automation and Test in Europe (DATE 2012), Dresden, 2012.
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[18]
2012 | Conference Paper | LibreCat-ID: 25767
A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms
D. He, W. Müller, in: 15th Euromicro Conference on Digital System Design (DSD), IEEE Xplore, 2012.
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[17]
2012 | Conference Paper | LibreCat-ID: 25744
Automated Source Code Annotation for Timing Analysis of Embedded Software
M. tech. M.M. Joy, M. Becker, E. Mathews, W. Müller, in: In Proceedings of Advanced Computing and Communications Conference 2012 (ADCOM 2012), IEEE, 2012.
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[16]
2012 | Journal Article | LibreCat-ID: 26038
SYSTEMC UVM VERIFICATION COMPONENTS
C. Kuznik, M.F. Oliveira, W. Müller, Design, Automation and Test in Europe DATE (2012).
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[15]
2012 | Conference Paper | LibreCat-ID: 26022
Binary Mutation Testing Through Dynamic Translation
M. Becker, C. Kuznik, M. tech. M.M. Joy, T. Xie, W. Müller, in: 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2012.
LibreCat | Download (ext.)
 
[14]
2011 | Conference Paper | LibreCat-ID: 26667
Aspect enhanced functional coverage driven verification in the SystemC HDVL
C. Kuznik, W. Müller, in: Proc. of the 8th International SoC Design Conference 2011 (ISOCC 2011), 2011.
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[13]
2011 | Conference Paper | LibreCat-ID: 26698
HDL-Mutation Based Simulation Data Generation by Propagation Guided Search
T. Xie, W. Müller, in: Proceedings of the 14th Euromicro Conference on Digital System Design (DSD), 2011.
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[12]
2011 | Conference Paper | LibreCat-ID: 26713
A Reconfiguration Approach for Fault-Tolerant FlexRay Networks
K. Klobedanz, A. König, W. Müller, in: Proceedings of Design, Automation, Test Europe - DATE2011, IEEE Computer Society Press, Grenoble, France, 2011.
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[11]
2011 | Conference Paper | LibreCat-ID: 26714
Self-Reconfiguration for Fault-Tolerant FlexRay Networks
K. Klobedanz, A. König, W. Müller, A. Rettberg, in: Second IEEE Workshop on Self-Organizing Real-Time Systems - SORT 2011, IEEE Computer Society Press, Newport Beach, California, USA, 2011.
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[10]
2011 | Conference Paper | LibreCat-ID: 26669
IP-XACT based System Level Mutation Testing
T. Xie, W. Müller, in: Proceedings of the 16th IEEE International High Level Design Validation and Test Workshop (HLDVT), 2011.
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[9]
2011 | Book Chapter | LibreCat-ID: 26695
Extending UML for Electronic Systems Design: A Code Generation Perspective
Y. Vanderperren, W. Müller, D. He, F. Mischkalla, W. Dahaene, in: G. Nicolescu, I. O’Connor, C. Piguet (Eds.), Design Technology for Heterogeneous Embedded Systems, 1st Edition. Auflage, Springer Verlag, 2011.
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[8]
2011 | Conference Paper | LibreCat-ID: 26710
Virtual Prototyping softwareintensiver mechatronischer Systeme – Eine Fallstudie
M. Becker, H. Zabel, W. Müller, A. Elfeky, A. DiPasquale, in: 8. Paderborner Workshop Entwurf Mechatronischer Systeme, Band 294, Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn, 2011, pp. 315–327.
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[7]
2011 | Conference Paper | LibreCat-ID: 26715
Functional Coverage-driven Verification with SystemC on Multiple Level of Abstraction
C. Kuznik, W. Müller, in: Proceedings of DVCON , 2011.
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[6]
2011 | Conference Paper | LibreCat-ID: 26784
Synchronisation eines SystemC Restbus-Simulators mit einem Hardware-In-the-Loop FlexRay Netzwerk
G.B. Gnokam Defo, W. Müller, in: Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV), 2011.
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[5]
2011 | Conference Paper | LibreCat-ID: 26789
Native binary mutation analysis for embedded software and virtual prototypes in SystemC
C. Kuznik, W. Müller, in: Proceedings of the 17th IEEE Pacific Rim International Symposium on Dependable Computing, 2011.
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[4]
2011 | Conference Paper | LibreCat-ID: 26716
A Retargetable SysML-based Front-End for High-Level Synthesis
F. Mischkalla, D. He, W. Müller, in: Proceedings of 2nd Workshop on Model Based Engineering for Embedded Systems Design (M-BED), 2011.
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[3]
2011 | Journal Article | LibreCat-ID: 26705
Verification Closure of SystemC Designs with Functional Coverage
C. Kuznik, W. Müller, North American SystemC User Group Meeting (16th) (2011).
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[2]
2011 | Conference Paper | LibreCat-ID: 26717
A SysML-based Framework with QEMU-SystemC Code Generation
D. He, F. Mischkalla, W. Müller, in: Proceedings of 1st International QEMU Users Forum, 2011.
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[1]
1998 | Book | LibreCat-ID: 23938
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
W. Müller, F.-J. Rammig, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Heinz Nixdorf Institut, Universität Paderborn, 1998.
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72 Publications

Mark all

[72]
2021 | Conference Paper | LibreCat-ID: 23992
Register and Instruction Coverage Analysis for Different RISC-V ISA Modules
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021), 2021.
LibreCat
 
[71]
2020 | Conference Paper | LibreCat-ID: 24027
A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, Stuttgart, DE, 2020.
LibreCat | Files available
 
[70]
2019 | Conference Paper | LibreCat-ID: 24058
RISC-V Extensions for Bit Manipulation Instructions
B. Koppelmann, P. Adelt, W. Müller, C. Scheytt, in: 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Rhodos, Griechenland, 2019.
LibreCat | Files available | DOI
 
[69]
2019 | Conference Paper | LibreCat-ID: 24060
Analyse sicherheitskritischer Software für RISC-V Prozessoren
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019), Kaiserslautern, DE, 2019.
LibreCat | Files available
 
[68]
2019 | Conference Paper | LibreCat-ID: 24061
QEMU for Dynamic Memory Analysis of Security Sensitive Software
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, B. Driessen, in: 2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019, Florence, Italy, 2019, pp. 32–34.
LibreCat | Files available
 
[67]
2019 | Journal Article | LibreCat-ID: 24063
QEMU Support for RISC-V: Current State and Future Releases
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, 2nd International Workshop on RISC-V Research Activities (Presentation) (2019).
LibreCat | Files available
 
[66]
2018 | Journal Article | LibreCat-ID: 24194
Current and Future RISC-V Activities for Virtual Prototyping and Chip Design
P. Adelt, B. Koppelmann, W. Müller, International Workshop on RISC-V Research Activities Presentation (2018).
LibreCat | Files available
 
[65]
2018 | Conference Paper | LibreCat-ID: 24196
Analog fault simulation automation at schematic level with random sampling techniques
L. Wu, M.K. Hussain, S. Abughannam, W. Müller, C. Scheytt, W. Ecker, in: 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)) , IEEE, Italy/Taormina, 2018.
LibreCat | Files available | DOI
 
[64]
2017 | Conference Paper | LibreCat-ID: 24224
ANALISA - A Tool for Static Instruction Set Analysis
P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, C. Scheytt, in: Design Automation and Testing in Europe (DATE), University Booth Interactive Presentation, Lausanne, CH, 2017.
LibreCat | Files available
 
[63]
2017 | Conference Paper | LibreCat-ID: 25069
ANALISA - A Tool for Static Instruction Set Analysis
P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, J.C. Scheytt, in: University Booth Interactive Presentation (Ed.), Design Automation and Testing in Europe (DATE), 2017.
LibreCat
 
[62]
2017 | Conference Paper | LibreCat-ID: 24225
An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries
P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, C. Scheytt, in: 2nd Workshop on Resiliency in Embedded Electronic Systems (REES) , Lausanne, Switzerland, 2017, p. 44.
LibreCat | Files available
 
[61]
2017 | Conference Paper | LibreCat-ID: 24220
Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen
P. Adelt, B. Koppelmann, W. Müller, D. Mueller-Gritschneder, B. Kleinjohann, C. Scheytt, in: Tagungsband des Wissenschaftsforums Intelligente Technische Systeme, Verlagsschriftenreihe des Heinz Nixdorf Instituts, Germany, Paderborn, 2017.
LibreCat | Files available | DOI
 
[60]
2017 | Conference Paper | LibreCat-ID: 24223
SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study
L. Wu, S. Abughannam, W. Müller, C. Scheytt, W. Ecker, in: 2nd Workshop on Resiliency in Embedded Electronic Systems (REES), Lausanne, Switzerland, 2017, p. 68.
LibreCat | Files available
 
[59]
2016 | Conference Paper | LibreCat-ID: 24263
Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study
S. Abughannam, L. Wu, W. Müller, C. Scheytt, in: Analog 2016 - VDE, 2016.
LibreCat
 
[58]
2016 | Conference Paper | LibreCat-ID: 24264
Fast Dynamic Fault Injection for Virtual Microcontroller Platforms
P. Adelt, B. Koppelmann, W. Müller, M. Becker, B. Kleinjohann, C. Scheytt, in: Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC), Tallin, Estonia, 2016.
LibreCat | DOI
 
[57]
2015 | Conference Paper | LibreCat-ID: 24289
On the Correlation of HW Faults and SW Errors
W. Müller, L. Wu, C. Scheytt, M. Becker, S. Schoenberg, in: D. Mueller-Gritschneder, W. Müller, S. Mitra (Eds.), Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014), Amsterdam, Netherland, 2015.
LibreCat
 
[56]
2014 | Conference Paper | LibreCat-ID: 25145
Virtual Platforms for Model-Based Design of Dependable Cyber-Physical System Software
M. Becker, C. Kuznik, W. Müller, in: 17th Euromicro Conference on Digital Systems Design (DSD), 2014.
LibreCat
 
[55]
2014 | Journal Article | LibreCat-ID: 25164
HeroeS³ -- A Framework for Heterogeneous Software-Intensive System Design with SystemC
M. Becker, W. Müller, J. Stroop, U. Kiffmeier, Design, Automation and Test in Europe DATE, University Booth, Dresden (2014).
LibreCat
 
[54]
2014 | Conference Paper | LibreCat-ID: 25169
Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges
J.-H. Oetjens, M. Becker, C. Kuznik, W. Müller, in: Design Automation Conference (DAC), 2014.
LibreCat
 
[53]
2014 | Journal Article | LibreCat-ID: 24302
Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU
B. Koppelmann, B. Messidat, M. Becker, C. Kuznik, W. Müller, C. Scheytt, Design and Verification Conference (DVCON EUROPE) (2014).
LibreCat
 
[52]
2014 | Conference Paper | LibreCat-ID: 25146
Source code annotated memory leak detection for soft real time embedded systems with resource constraints
M. tech. M.M. Joy, W. Müller, F.-J. Rammig, in: 12th IEEE International Conference on Embedded Computing, 2014.
LibreCat
 
[51]
2014 | Conference Paper | LibreCat-ID: 25161
Portierung der TriCore-Architektur auf QEMU
B. Koppelmann, M. Becker, W. Müller, in: 17. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2014) , 2014.
LibreCat
 
[50]
2014 | Conference Paper | LibreCat-ID: 25166
Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM
C. Kuznik, W. Müller, in: 26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, 2014.
LibreCat
 
[49]
2014 | Journal Article | LibreCat-ID: 24309
Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure
C. Kuznik, W. Müller, Design, Automation and Test in Europe DATE, University Booth, Dresden (2014).
LibreCat
 
[48]
2014 | Conference Paper | LibreCat-ID: 24311
Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges
J.-H. Oetjens, M. Becker, C. Kuznik, W. Müller, in: Design Automation Conference (DAC), 2014.
LibreCat | DOI
 
[47]
2014 | Journal Article | LibreCat-ID: 25117
Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU
B. Koppelmann, B. Messidat, M. Becker, C. Kuznik, W. Müller, J.C. Scheytt, Design and Verification Conference (DVCON EUROPE) (2014).
LibreCat
 
[46]
2014 | Conference Paper | LibreCat-ID: 25155
Fault Effect Modeling in a Heterogeneous SystemC Virtual Platform Framework for Cyber-Physical Systems
M. Becker, C. Kuznik, W. Müller, in: ACM/IEEE 5th International Conference on Cyber-Physical Systems, 2014.
LibreCat
 
[45]
2014 | Journal Article | LibreCat-ID: 25162
Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure
C. Kuznik, W. Müller, Design, Automation and Test in Europe DATE, University Booth, Dresden (2014).
LibreCat
 
[44]
2014 | Conference Paper | LibreCat-ID: 24305
Architectural Low-Power Design Using Transaction-Based System Modeling and Simulation
F. Mischkalla, W. Müller, in: Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), IEEE, Greece, 2014.
LibreCat | DOI
 
[43]
2014 | Conference Paper | LibreCat-ID: 25120
Architectural Low-Power Design Using Transaction-Based System Simulation
F. Mischkalla, W. Müller, in: Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), IEEE, 2014.
LibreCat
 
[42]
2014 | Conference Paper | LibreCat-ID: 25144
Advanced SoC Virtual Prototyping for System-Level Power Planning and Validation
F. Mischkalla, W. Müller, in: PATMOS 2014, Palma de Mallorca, Spain, 2014.
LibreCat
 
[41]
2014 | Journal Article | LibreCat-ID: 25151
An Assisted Single Source Verification Metric Model Code Generation Methodology
C. Kuznik, B.G. Defo, W. Müller, Electronic System Level Synthesis Conference (ESLSyn) (2014).
LibreCat
 
[40]
2014 | Conference Paper | LibreCat-ID: 25163
Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung
C. Kuznik, B.G. Defo, W. Müller, in: 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) , 2014.
LibreCat
 
[39]
2013 | Conference Paper | LibreCat-ID: 25284
Efficient Power Intent Validation Using Loosely-Timed Simulation Models
F. Mischkalla, W. Müller, in: 23rd International Workshop on Power And Timing Modeling, Optimization and Simulation, Sep. 2013, 2013.
LibreCat
 
[38]
2013 | Conference Paper | LibreCat-ID: 25291
HeroeS: Virtual Platform Driven Integration of Heterogeneous Software Components for Multi-Core Real-Time Architectures
M. Becker, U. Kiffmeier, W. Müller, in: 16th IEEE Computer Society Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2013.
LibreCat
 
[37]
2013 | Conference Paper | LibreCat-ID: 25614
SC OVM: An Advanced SystemC Library for OVM-based Verification
C. Kuznik, M. F. S. Oliveira, W. Müller, in: Open SANITAS SystemC Verification Workshop, 2013.
LibreCat
 
[36]
2013 | Newspaper Article | LibreCat-ID: 25615
Informationstechnik spart Ressourcen
G. Engels, C. Gerth, L. Kleinjohann, B. Kleinjohann, W. Müller, ForschungsForum Paderborn (2013).
LibreCat
 
[35]
2013 | Book Chapter | LibreCat-ID: 25743
Methods for the Design and Development
H. Anacker, M. Dellnitz, K. Flaßkamp, S. Grösbrink, P. Hartmann, C. Heinzemann, C. Horenkamp, L. Kleinjohann, B. Kleinjohann, S. Korf, M. Krüger, W. Müller, S. Ober-Blöbaum, S. Oberthür, M. Porrmann, C. Priesterjahn, W. Radkowski, C. Rasche, J. Rieke, M. Ringkamp, K. Stahl, D. Steenken, J. Stöcklein, R. Timmermann, A. Trächtler, K. Witting, T. Xie, S. Ziegert, in: Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future, Springer-Verlag, Heidelberg, 2013, pp. 187–356.
LibreCat
 
[34]
2013 | Conference Paper | LibreCat-ID: 25270
Early Phase Memory Leak Detection in Embedded Software Designs with Virtual Memory Management Model
M. tech. M.M. Joy, W. Müller, F.-J. Rammig, in: Proceedings of AVICPS 2013, Dez. 2013 IEEE Computer Society, Linköping University Electronic Press, 2013.
LibreCat
 
[33]
2013 | Conference Paper | LibreCat-ID: 25612
Funktionale Verifikation von Low-Power Designs unter Verwendung Virtueller Prototypen
F. Mischkalla, W. Müller, in: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013.
LibreCat
 
[32]
2013 | Conference Paper | LibreCat-ID: 25271
AN ENERGY-EFFICIENT HEURISTIC FOR HARD REAL- TIME SYSTEM ON MULTI-CORE PROCESSORS
D. He, W. Müller, in: Proceedings of International Conference on Applied Computing (AC), 2013.
LibreCat
 
[31]
2013 | Conference Paper | LibreCat-ID: 25606
SystemC Verification Components - An enhanced OVM/UVM for SystemC
C. Kuznik, M. F. S. Oliveira, W. Müller, in: EdaWorkshop 13, 2013.
LibreCat
 
[30]
2013 | Conference Paper | LibreCat-ID: 25620
Systematic Application of UCIS to Improve the Automation on Verification Closure
C. Kuznik, M.F. Oliveira, B. Defo, W. Müller, in: Proceedings of DVCON, 2013.
LibreCat
 
[29]
2013 | Conference Paper | LibreCat-ID: 25632
Fault-Tolerant Deployment of Real-Time Software in AUTOSAR ECU Networks
K. Klobedanz, J. Jatzkowski, A. Rettberg, W. Müller, in: International Embedded Systems Symposium (IESS) 2013, Springer, 2013.
LibreCat
 
[28]
2013 | Journal Article | LibreCat-ID: 25740
A heuristic energy-aware approach for hard real-time systems on multi-core platforms
D. He, W. Müller, Microprocessors and Microsystems - Embedded Hardware Design 37(6-7) (2013) 845–857.
LibreCat
 
[27]
2012 | Conference Paper | LibreCat-ID: 25758
XEMU: An Efficient QEMU Based Binary Mutation Testing Framework for Embedded Software
M. Becker, D. Baldin, C. Kuznik, M. tech. M.M. Joy, T. Xie, W. Müller, in: EMSOFT’12: Teenth ACM International Conference on Embedded Software 2012 Proceedings , 2012.
LibreCat
 
[26]
2012 | Conference Paper | LibreCat-ID: 26023
Enhanced Schedulability Analysis of Hard Real-Time Systems on Power Manageable Multi-Core Platforms
D. He, W. Müller, in: Third International Symposium on Advances in Embedded Systems and Applications (ESA-2012), IEEE Xplore, 2012.
LibreCat
 
[25]
2012 | Conference Paper | LibreCat-ID: 26080
XEMU: A QEMU Based Binary Mutation Testing Framework
M. Becker, C. Kuznik, M. tech. M. Joy, T. Xie, W. Müller, in: Design, Automation and Test in Europe DATE, University Booth, Dresden, 2012.
LibreCat
 
[24]
2012 | Conference Paper | LibreCat-ID: 26092
Virtual Prototyping of Cyber-Physical Systems
W. Müller, M. Becker, H. Zabel, A. Elfeky, A. DiPasquale, in: In Proceedings of 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012, Sydney, 2012.
LibreCat
 
[23]
2012 | Conference Paper | LibreCat-ID: 25761
The System Verification Methodology for Advanced TLM Verification
M.F. Oliveira, C. Kuznik, H.M. Le, D. Große, F. Haedicke, W. Müller, R. Drechsler, W. Ecker, V. Esen, in: CODES/ISSS ’12: Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Proceedings, 2012.
LibreCat
 
[22]
2012 | Conference Paper | LibreCat-ID: 26024
Compilation of Methodologies to Speed up the Verification Process at System Level
S. Radke, S. Rülke, M.F. Oliveira, C. Kuznik, W. Müller, W. Ecker, V. Esen, S. Hufnagel, N. Bannow, J.-H. Oetjens, H. Brazdrum, P. Janssen, H.M. Le, D. Große, F. Haedicke, R. Drechsler, G. Koch, A. Burger, O. Bringmann, W. Rosenstiel, R. Görgen, in: EdaWorkshop 12, 2012.
LibreCat | Download (ext.)
 
[21]
2012 | Conference Paper | LibreCat-ID: 26031
Online Energy-Efficient Hard Real-Time Scheduling for Component Oriented Systems
D. He, W. Müller, in: 2012 IEEE 15th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC), IEEE Xplore, 2012.
LibreCat
 
[20]
2012 | Conference Paper | LibreCat-ID: 26036
A SystemC Library for Advanced TLM Verification
M.F. Oliveira, C. Kuznik, W. Müller, W. Ecker, V. Esen, in: Proceeding of Design and Verification Conference (DVCON), 2012.
LibreCat
 
[19]
2012 | Conference Paper | LibreCat-ID: 26079
MOUSSE: scaling MOdelling and verification to complex heterogeneoUS embedded Systems Evolution
M. Becker, G.B. Gnokam Defo, W. Müller, F. Fummi, G. Pravadelli, S. Vinco, in: Design, Automation and Test in Europe (DATE 2012), Dresden, 2012.
LibreCat
 
[18]
2012 | Conference Paper | LibreCat-ID: 25767
A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms
D. He, W. Müller, in: 15th Euromicro Conference on Digital System Design (DSD), IEEE Xplore, 2012.
LibreCat
 
[17]
2012 | Conference Paper | LibreCat-ID: 25744
Automated Source Code Annotation for Timing Analysis of Embedded Software
M. tech. M.M. Joy, M. Becker, E. Mathews, W. Müller, in: In Proceedings of Advanced Computing and Communications Conference 2012 (ADCOM 2012), IEEE, 2012.
LibreCat
 
[16]
2012 | Journal Article | LibreCat-ID: 26038
SYSTEMC UVM VERIFICATION COMPONENTS
C. Kuznik, M.F. Oliveira, W. Müller, Design, Automation and Test in Europe DATE (2012).
LibreCat
 
[15]
2012 | Conference Paper | LibreCat-ID: 26022
Binary Mutation Testing Through Dynamic Translation
M. Becker, C. Kuznik, M. tech. M.M. Joy, T. Xie, W. Müller, in: 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2012.
LibreCat | Download (ext.)
 
[14]
2011 | Conference Paper | LibreCat-ID: 26667
Aspect enhanced functional coverage driven verification in the SystemC HDVL
C. Kuznik, W. Müller, in: Proc. of the 8th International SoC Design Conference 2011 (ISOCC 2011), 2011.
LibreCat
 
[13]
2011 | Conference Paper | LibreCat-ID: 26698
HDL-Mutation Based Simulation Data Generation by Propagation Guided Search
T. Xie, W. Müller, in: Proceedings of the 14th Euromicro Conference on Digital System Design (DSD), 2011.
LibreCat
 
[12]
2011 | Conference Paper | LibreCat-ID: 26713
A Reconfiguration Approach for Fault-Tolerant FlexRay Networks
K. Klobedanz, A. König, W. Müller, in: Proceedings of Design, Automation, Test Europe - DATE2011, IEEE Computer Society Press, Grenoble, France, 2011.
LibreCat
 
[11]
2011 | Conference Paper | LibreCat-ID: 26714
Self-Reconfiguration for Fault-Tolerant FlexRay Networks
K. Klobedanz, A. König, W. Müller, A. Rettberg, in: Second IEEE Workshop on Self-Organizing Real-Time Systems - SORT 2011, IEEE Computer Society Press, Newport Beach, California, USA, 2011.
LibreCat
 
[10]
2011 | Conference Paper | LibreCat-ID: 26669
IP-XACT based System Level Mutation Testing
T. Xie, W. Müller, in: Proceedings of the 16th IEEE International High Level Design Validation and Test Workshop (HLDVT), 2011.
LibreCat
 
[9]
2011 | Book Chapter | LibreCat-ID: 26695
Extending UML for Electronic Systems Design: A Code Generation Perspective
Y. Vanderperren, W. Müller, D. He, F. Mischkalla, W. Dahaene, in: G. Nicolescu, I. O’Connor, C. Piguet (Eds.), Design Technology for Heterogeneous Embedded Systems, 1st Edition. Auflage, Springer Verlag, 2011.
LibreCat
 
[8]
2011 | Conference Paper | LibreCat-ID: 26710
Virtual Prototyping softwareintensiver mechatronischer Systeme – Eine Fallstudie
M. Becker, H. Zabel, W. Müller, A. Elfeky, A. DiPasquale, in: 8. Paderborner Workshop Entwurf Mechatronischer Systeme, Band 294, Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn, 2011, pp. 315–327.
LibreCat
 
[7]
2011 | Conference Paper | LibreCat-ID: 26715
Functional Coverage-driven Verification with SystemC on Multiple Level of Abstraction
C. Kuznik, W. Müller, in: Proceedings of DVCON , 2011.
LibreCat
 
[6]
2011 | Conference Paper | LibreCat-ID: 26784
Synchronisation eines SystemC Restbus-Simulators mit einem Hardware-In-the-Loop FlexRay Netzwerk
G.B. Gnokam Defo, W. Müller, in: Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV), 2011.
LibreCat
 
[5]
2011 | Conference Paper | LibreCat-ID: 26789
Native binary mutation analysis for embedded software and virtual prototypes in SystemC
C. Kuznik, W. Müller, in: Proceedings of the 17th IEEE Pacific Rim International Symposium on Dependable Computing, 2011.
LibreCat
 
[4]
2011 | Conference Paper | LibreCat-ID: 26716
A Retargetable SysML-based Front-End for High-Level Synthesis
F. Mischkalla, D. He, W. Müller, in: Proceedings of 2nd Workshop on Model Based Engineering for Embedded Systems Design (M-BED), 2011.
LibreCat
 
[3]
2011 | Journal Article | LibreCat-ID: 26705
Verification Closure of SystemC Designs with Functional Coverage
C. Kuznik, W. Müller, North American SystemC User Group Meeting (16th) (2011).
LibreCat
 
[2]
2011 | Conference Paper | LibreCat-ID: 26717
A SysML-based Framework with QEMU-SystemC Code Generation
D. He, F. Mischkalla, W. Müller, in: Proceedings of 1st International QEMU Users Forum, 2011.
LibreCat
 
[1]
1998 | Book | LibreCat-ID: 23938
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
W. Müller, F.-J. Rammig, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Heinz Nixdorf Institut, Universität Paderborn, 1998.
LibreCat
 

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