A Retargetable SysML-based Front-End for High-Level Synthesis

UML profiles like SysML and MARTE have been a major research topic in electronic system design, but are mainly applied for specification and analysis in early design phases. High-Level Synthesis (HLS), however, addresses the physical implementation aspect of electronic systems, and thus leads to different requirements on the accuracy of models. For this, modular interfaces are a novel object-oriented synthesizable technique to overcome the conflict between a higher degree of abstraction and necessary details for further synthesis. In this paper, we present our approach to use SysML as an adequate modeling language for modular interfaces and C/C++/SystemC-based HLS. We extended SysML with annotations for synthesizable SystemC and high-level synthesis constraints and implemented a code generation scheme to achieve design flow automation. Based on the SysML editor Artisan Studio and an industrial case study, we demonstrate the applicability of SysML as a retargetable front-end for HLS design flows.