HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory

A.R. Tareen, M. Meyer, C. Plessl, T. Kenter, in: 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2024.

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Conference Paper | Published | English
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Proceedings Title
2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
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35
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Tareen AR, Meyer M, Plessl C, Kenter T. HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory. In: 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). Vol 35. IEEE; 2024. doi:10.1109/fccm60383.2024.00014
Tareen, A. R., Meyer, M., Plessl, C., & Kenter, T. (2024). HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory. 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 35. https://doi.org/10.1109/fccm60383.2024.00014
@inproceedings{Tareen_Meyer_Plessl_Kenter_2024, title={HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory}, volume={35}, DOI={10.1109/fccm60383.2024.00014}, booktitle={2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Tareen, Abdul Rehman and Meyer, Marius and Plessl, Christian and Kenter, Tobias}, year={2024} }
Tareen, Abdul Rehman, Marius Meyer, Christian Plessl, and Tobias Kenter. “HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory.” In 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Vol. 35. IEEE, 2024. https://doi.org/10.1109/fccm60383.2024.00014.
A. R. Tareen, M. Meyer, C. Plessl, and T. Kenter, “HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory,” in 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2024, vol. 35, doi: 10.1109/fccm60383.2024.00014.
Tareen, Abdul Rehman, et al. “HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory.” 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), vol. 35, IEEE, 2024, doi:10.1109/fccm60383.2024.00014.

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