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9762 Publications
2014 | Conference Paper | LibreCat-ID: 10621
Anwer J, Platzner M, Meisner S. FPGA Redundancy Configurations: An Automated Design Space Exploration. In: Reconfigurable Architectures Workshop (RAW). RAW. ; 2014. doi:10.1109/IPDPSW.2014.37
LibreCat
| DOI
2014 | Bachelorsthesis | LibreCat-ID: 10627
Bockhorn A. Echtzeit Klassifikation von SEMG Signalen Mit Einem Low-Cost DSP Evaluation Board. Paderborn University; 2014.
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2014 | Conference Paper | LibreCat-ID: 10632
Boschmann A, Platzner M. A computer vision-based approach to high density EMG pattern recognition using structural similarity. In: Proc. MyoElectric Controls Symposium (MEC). ; 2014.
LibreCat
2014 | Conference Paper | LibreCat-ID: 10633
Boschmann A, Platzner M. Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity. In: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC). ; 2014.
LibreCat
2014 | Mastersthesis | LibreCat-ID: 10640
Brand M. A Generalized Loop Accelerator Implemented as a Coarse-Grained Array. Paderborn University; 2014.
LibreCat
2014 | Mastersthesis | LibreCat-ID: 10645
Damschen M. Easy-to-Use-on-the-Fly Binary Program Acceleration on Many-Cores. Paderborn University; 2014.
LibreCat
2014 | Conference Paper | LibreCat-ID: 10654
Glette K, Kaufmann P. Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System. In: IEEE Congress on Evolutionary Computation (CEC). ; 2014.
LibreCat
2014 | Bachelorsthesis | LibreCat-ID: 10665
Hagedorn C. Entwicklung Einer Codegrößenoptimierten Softwarebibliothek Für 8-Bit Mikrocontroller in Netzunabhängigen Notleuchten. Paderborn University; 2014.
LibreCat
2014 | Conference Paper | LibreCat-ID: 10674
Ho N, Kaufmann P, Platzner M. A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. In: 24th Intl. Conf. on Field Programmable Logic and Applications (FPL). ; 2014:1-4. doi:10.1109/FPL.2014.6927437
LibreCat
| DOI
2014 | Conference Paper | LibreCat-ID: 10677
Ho N, Kaufmann P, Platzner M. Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. In: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES). ; 2014:31-37. doi:10.1109/ICES.2014.7008719
LibreCat
| DOI
2014 | Bachelorsthesis | LibreCat-ID: 10679
König F. EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer Virtuellen Prothese. Paderborn University; 2014.
LibreCat
2014 | Mastersthesis | LibreCat-ID: 10701
Koch B. Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University; 2014.
LibreCat
2014 | Mastersthesis | LibreCat-ID: 10715
Mittendorf R. Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading and FPGAs. Paderborn University; 2014.
LibreCat
2014 | Bachelorsthesis | LibreCat-ID: 10732
Rüthing C. The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores. Paderborn University; 2014.
LibreCat
2014 | Dissertation | LibreCat-ID: 10733
Schäfers L. Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH; 2014.
LibreCat
2014 | Conference Paper | LibreCat-ID: 10738
Shen C, Kaufmann P, Braun M. Optimizing the Generator Start-up Sequence After a Power System Blackout. In: IEEE Power and Energy Society General Meeting (IEEE GM). ; 2014.
LibreCat
2014 | Conference Paper | LibreCat-ID: 10739
Shen C, Kaufmann P, Braun M. A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm. In: Power Systems Computation Conference (PSCC). IEEE; 2014.
LibreCat
2014 | Mastersthesis | LibreCat-ID: 10744
Surmund S. Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University; 2014.
LibreCat
2014 | Book | LibreCat-ID: 10756
I. Esparcia-Alc{\’a}zar A, Eiben AE, Agapitos A, et al. Applications of Evolutionary Computation - 17th European Conference, EvoApplications. Vol 8602. Granada, Spain: Springer; 2014.
LibreCat
2014 | Conference Paper | LibreCat-ID: 10764
Anwer J, Platzner M. Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). IEEE; 2014:177-184. doi:10.1109/DFT.2014.6962108
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| DOI