FPGA Redundancy Configurations: An Automated Design Space Exploration

J. Anwer, M. Platzner, S. Meisner, in: Reconfigurable Architectures Workshop (RAW), 2014.

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Reconfigurable Architectures Workshop (RAW)
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Anwer J, Platzner M, Meisner S. FPGA Redundancy Configurations: An Automated Design Space Exploration. In: Reconfigurable Architectures Workshop (RAW). RAW. ; 2014. doi:10.1109/IPDPSW.2014.37
Anwer, J., Platzner, M., & Meisner, S. (2014). FPGA Redundancy Configurations: An Automated Design Space Exploration. In Reconfigurable Architectures Workshop (RAW). https://doi.org/10.1109/IPDPSW.2014.37
@inproceedings{Anwer_Platzner_Meisner_2014, series={RAW}, title={FPGA Redundancy Configurations: An Automated Design Space Exploration}, DOI={10.1109/IPDPSW.2014.37}, booktitle={Reconfigurable Architectures Workshop (RAW)}, author={Anwer, Jahanzeb and Platzner, Marco and Meisner, Sebastian}, year={2014}, collection={RAW} }
Anwer, Jahanzeb, Marco Platzner, and Sebastian Meisner. “FPGA Redundancy Configurations: An Automated Design Space Exploration.” In Reconfigurable Architectures Workshop (RAW). RAW, 2014. https://doi.org/10.1109/IPDPSW.2014.37.
J. Anwer, M. Platzner, and S. Meisner, “FPGA Redundancy Configurations: An Automated Design Space Exploration,” in Reconfigurable Architectures Workshop (RAW), 2014.
Anwer, Jahanzeb, et al. “FPGA Redundancy Configurations: An Automated Design Space Exploration.” Reconfigurable Architectures Workshop (RAW), 2014, doi:10.1109/IPDPSW.2014.37.

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