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364 Publications

2011 | Mastersthesis | LibreCat-ID: 10736
Schwabe, A. (2011). Analysis of Algorithmic Approaches for Temporal Partitioning. Paderborn University.

2011 | Mastersthesis | LibreCat-ID: 10750
Welp, D. (2011). User Space Scheduling for Heterogeneous Systems. Paderborn University.

2011 | Bachelorsthesis | LibreCat-ID: 10680
Kassner, H. (2011). MPI-CUDA Codegenerierung für Nanophoton Simulationen auf Clustern. Paderborn University.

2011 | Bachelorsthesis | LibreCat-ID: 10678
Ikonomakis, N. (2011). PinSim: Schnelle Simulation mit Pintools. Paderborn University.

2011 | Book Chapter | LibreCat-ID: 10748
Walker, J. A., Miller, J. F., Kaufmann, P., & Platzner, M. (2011). Problem Decomposition in Cartesian Genetic Programming. In Cartesian Genetic Programming (pp. 35–99). Springer Berlin Heidelberg.

2011 | Conference Paper | LibreCat-ID: 2200
Kenter, T., Platzner, M., Plessl, C., & Kauschke, M. (2011). Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. In Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA) (pp. 177–180). New York, NY, USA: ACM.
LibreCat | DOI

2011 | Book Chapter | LibreCat-ID: 10737
Sekanina, L., Walker, J. A., Kaufmann, P., Plessl, C., & Platzner, M. (2011). Evolution of Electronic Circuits. In Cartesian Genetic Programming (pp. 125–179). Springer Berlin Heidelberg.

2011 | Conference Paper | LibreCat-ID: 2193
Beisel, T., Wiersema, T., Plessl, C., & Brinkmann, A. (2011). Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) (pp. 223–226). IEEE Computer Society.
LibreCat | DOI

2011 | Journal Article | LibreCat-ID: 2201
Schumacher, T., Süß, T., Plessl, C., & Platzner, M. (2011). FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. Int. Journal of Recon- Figurable Computing (IJRC).
LibreCat | DOI

2011 | Conference Paper | LibreCat-ID: 2198
Grad, M., & Plessl, C. (2011). Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. In Proc. Reconfigurable Architectures Workshop (RAW) (pp. 278–285). IEEE Computer Society.
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