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461 Publications
2026 | Journal Article | LibreCat-ID: 61152
Umuroglu, Y., Berganski, C., Jentzsch, F., Danilowicz, M., Kryjak, T., Bezaitis, C., Sjalander, M., Colbert, I., Preusser, T., Petri-Koenig, J., & Blott, M. (n.d.). SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators. ACM Transactions on Reconfigurable Technology and Systems. https://doi.org/10.1145/3807510
LibreCat
| DOI
2026 | Conference Paper | LibreCat-ID: 65501
Stasytis, L., Jentzsch, F., Preusser, T., Umuroglu, Y., Petri-Koenig, J., & István, Z. (2026). Heuristic & Expert-Guided Buffer Sizing for Neural Network Inference Applications on FPGAs. 2025 International Conference on Field Programmable Technology (ICFPT). https://doi.org/10.1109/icfpt67023.2025.00032
LibreCat
| DOI
2026 | Conference Paper | LibreCat-ID: 65500
Jentzsch, F., & Platzner, M. (2026). Empirical QoR Estimation Flow for Fast Design Space Exploration of DNN Dataflow Accelerators. 2025 International Conference on Field Programmable Technology (ICFPT). https://doi.org/10.1109/icfpt67023.2025.00044
LibreCat
| DOI
2025 | Conference Paper | LibreCat-ID: 64112
Jalil, F., Awais, M., Ahmed, Q. A., Mohammadi, H. G., Jungeblut, T., & Platzner, M. (2025). Deep&Wide: Achieving Area Efficiency in Scalable Approximate Accelerators. 2025 55th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W). https://doi.org/10.1109/dsn-w65791.2025.00048
LibreCat
| DOI
2025 | Conference Paper | LibreCat-ID: 64113
Hadipour, A. H., Jafari, A., Awais, M., & Platzner, M. (2025). A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation. 2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). https://doi.org/10.1109/ddecs63720.2025.11006769
LibreCat
| DOI
2025 | Journal Article | LibreCat-ID: 62020
Awais, M., Mohammadi, H. G., & Platzner, M. (2025). Design Space Exploration for Approximate Circuits via Checkpointing and DNN-Based Estimators. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 33(9), 2395–2405. https://doi.org/10.1109/tvlsi.2025.3559377
LibreCat
| DOI
2025 | Conference Paper | LibreCat-ID: 62019
Hadipour, A. H., Jafari, A., Awais, M., & Platzner, M. (2025). A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation. 2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). https://doi.org/10.1109/ddecs63720.2025.11006769
LibreCat
| DOI
2025 | Mastersthesis | LibreCat-ID: 62268
Bengaluru Amarnath, P. (2025). Design and Integration of Intra-Process Communication for ROS 2 into ReconROS. Paderborn University.
LibreCat
2024 | Journal Article | LibreCat-ID: 52686
Ahmed, Q. A., Wiersema, T., & Platzner, M. (2024). Post-configuration Activation of Hardware Trojans in FPGAs. Journal of Hardware and Systems Security. https://doi.org/10.1007/s41635-024-00147-5
LibreCat
| DOI
2024 | Conference Paper | LibreCat-ID: 54468
Awais, M., Ghasemzadeh Mohammadi, H., & Platzner, M. (2024). DeepApprox: Rapid Deep Learning based Design Space Exploration of Approximate Circuits via Check-pointing. To Apear in IEEE ISVLSI 2024. IEEE Computer Society Annual Symposium on VLSI, Knoxville, Tennessee, USA.
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