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226 Publications


2010 | Mastersthesis | LibreCat-ID: 10752
Scheduling Support for Heterogeneous Hardware Accelerators under Linux
T. Wiersema, Scheduling Support for Heterogeneous Hardware Accelerators under Linux, Paderborn University, 2010.
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2010 | Bachelorsthesis | LibreCat-ID: 10649
Soft Microprocessors with tightly coupled Application-Specific Coprocessors
D. Dridger, Soft Microprocessors with Tightly Coupled Application-Specific Coprocessors, Paderborn University, 2010.
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2010 | Conference Paper | LibreCat-ID: 2220
Configurable Processor Architectures: History and Trends
D. Andrews, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, p. 165.
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2010 | Journal Article | LibreCat-ID: 10694
Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial)
U. Kebschull, M. Platzner, J. Teich, IET Computers Digital Techniques 4 (2010) 157–158.
LibreCat | DOI
 

2010 | Conference Paper | LibreCat-ID: 2226
Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators
T. Beisel, M. Niekamp, C. Plessl, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010, pp. 65–72.
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2010 | Mastersthesis | LibreCat-ID: 10710
FPGA/CPU Multicore-Plattform für ReconOS/eCos
R. Meiche, FPGA/CPU Multicore-Plattform Für ReconOS/ECos, Paderborn University, 2010.
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2010 | Mastersthesis | LibreCat-ID: 10614
Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen
A. Agne, Virtuelle Speicherverwaltung Für Hardware Threads in Rekonfigurierbaren Systemen, Paderborn University, 2010.
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2010 | Bachelorsthesis | LibreCat-ID: 10657
Parallelization of the UCT Algorithm on HPC-Clusters
T. Graf, Parallelization of the UCT Algorithm on HPC-Clusters, Paderborn University, 2010.
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2009 | Conference Paper | LibreCat-ID: 2261
An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure
T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2009, pp. 338–344.
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2009 | Conference Paper | LibreCat-ID: 2350
IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing
T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–278.
LibreCat | DOI
 

2009 | Conference Paper | LibreCat-ID: 2262
EvoCaches: Application-specific Adaptation of Cache Mapping
P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 11–18.
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2009 | Mastersthesis | LibreCat-ID: 10749
Coarse-grained CGP Model using Xilinx Virtex5 DSP48E Functional Units
A. Warkentin, Coarse-Grained CGP Model Using Xilinx Virtex5 DSP48E Functional Units, Paderborn University, 2009.
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2009 | Mastersthesis | LibreCat-ID: 10702
Evolvable Robot Controller
A. Kostin, Evolvable Robot Controller, Paderborn University, 2009.
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2009 | Conference Paper | LibreCat-ID: 2263
Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX
M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, USA, 2009, pp. 319–322.
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2009 | Conference Paper | LibreCat-ID: 2238
Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000
T. Schumacher, T. Süß, C. Plessl, M. Platzner, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 119–124.
LibreCat | DOI
 

2009 | Mastersthesis | LibreCat-ID: 10746
Compiler for a Custom Instruction Set CPU
M. Tofall, Compiler for a Custom Instruction Set CPU, Paderborn University, 2009.
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2009 | Bachelorsthesis | LibreCat-ID: 10753
Implementierung von Kryptographie-Hardwarebeschleunigern für das HW/SW-Betriebssystem ReconOS
B. Wildenhain, Implementierung von Kryptographie-Hardwarebeschleunigern Für Das HW/SW-Betriebssystem ReconOS, Paderborn University, 2009.
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2009 | Journal Article | LibreCat-ID: 10703
ReconOS: Multithreaded Programming for Reconfigurable Computers
E. Lübbers, M. Platzner, ACM Transactions on Embedded Computing Systems 9 (2009) 8:1-8:33.
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2008 | Bachelorsthesis | LibreCat-ID: 10696
Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf
T. Knieper, Implementierung Und Bewertung Des Multikriteriellen Optimierungsverfahrens IBEA Für Den Automatisierten Schaltungsentwurf, Paderborn University, 2008.
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2008 | Bachelorsthesis | LibreCat-ID: 10641
Selbstoptimierender Cache-Kontroller
D. Breitlauch, Selbstoptimierender Cache-Kontroller, Paderborn University, 2008.
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