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15 Publications
2022 | Dissertation | LibreCat-ID: 29769 | 
Ahmed QA. Hardware Trojans in Reconfigurable Computing. Paderborn University, Paderborn, Germany; 2022. doi:10.17619/UNIPB/1-1271
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2021 | Dissertation | LibreCat-ID: 26746 |
Wiersema T. Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware. Paderborn University; 2021.
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2021 | Journal Article | LibreCat-ID: 27841
Jakobs M-C, Pauck F, Platzner M, Wehrheim H, Wiersema T. Software/Hardware Co-Verification for Custom Instruction Set Processors. IEEE Access. Published online 2021. doi:10.1109/ACCESS.2021.3131213
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2020 | Journal Article | LibreCat-ID: 17358
Witschen LM, Wiersema T, Platzner M. Proof-carrying Approximate Circuits. IEEE Transactions On Very Large Scale Integration Systems. 2020;28(9):2084-2088. doi:10.1109/TVLSI.2020.3008061
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2019 | Preprint | LibreCat-ID: 16853
Witschen LM, Ghasemzadeh Mohammadi H, Artmann M, Platzner M. Jump Search: A Fast Technique for the Synthesis of Approximate Circuits. Fourth Workshop on Approximate Computing (AxC 2019).
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2018 | Bachelorsthesis | LibreCat-ID: 1097
Jentzsch FP. Enforcing IP Core Connection Properties with Verifiable Security Monitors. Universität Paderborn; 2018.
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2014 | Conference Paper | LibreCat-ID: 36917
Kuznik C, Müller W, Defo GB. An Assisted Single Source Verification Metric Model Code Generation Methodology. In: ; 2014.
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2014 | Conference Paper | LibreCat-ID: 34585
Koppelmann B, Messidat B, Becker M, Müller W, Scheytt JC. Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. In: Proceedings of the Design and Verification Conference Europe (DVCON Europe). ; 2014.
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2008 | Conference Paper | LibreCat-ID: 2370
Woehrle M, Plessl C, Lim R, Beutel J, Thiele L. EvAnT: Analysis and Checking of event traces for Wireless Sensor Networks. In: IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC). IEEE Computer Society; 2008:201-208. doi:10.1109/SUTC.2008.24
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2007 | Conference Paper | LibreCat-ID: 2393
Beutel J, Dyer M, Lim R, et al. Automated Wireless Sensor Network Testing. In: Proc. Int. Conf. Networked Sensing Systems (INSS). IEEE; 2007:303-303. doi:10.1109/INSS.2007.4297445
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2004 | Conference Paper | LibreCat-ID: 39069
Flake S, Müller W. Past- and Future-Oriented Time-Bound Temporal Properties with OCL. In: Proceedings of SEFM´04. IEEE; 2004. doi:10.1109/SEFM.2004.1347516
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2002 | Conference Paper | LibreCat-ID: 39382
Müller W, Dömer R, Gerstlauer A. The Formal Execution Semantics of SpecC. In: Proceedings of the ISSS02. ; 2002. doi:10.1145/581199.581234
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2002 | Conference Paper | LibreCat-ID: 39403
Flake S, Müller W. Specification of Real-Time Properties for UML Models. In: Proceedings of HICSS-35. ; 2002. doi:10.1109/HICSS.2002.994469
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2001 | Conference Paper | LibreCat-ID: 39421
Müller W, Ruf J, Hoffmann DW, Gerlach J, Kropf T, Rosenstiehl W. The Simulation Semantics of SystemC. In: Proceedings of the Design, Automation, and Test in Europe (DATE’01). IEEE; 2001. doi:10.1109/DATE.2001.915002
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1995 | Book Chapter | LibreCat-ID: 34448
Börger E, Glässer U, Müller W. A Formal Definition of an Abstract VHDL’93 Simulator by EA-Machines. In: Delgado Kloos C, Breuer PT, eds. Semantics of VHDL. Kluwer Academic Publishers; 1995:107-139. doi:10.1007/978-1-4615-2237-9_5
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