18 Publications

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[18]
2023 | Conference Paper | LibreCat-ID: 45776
Ecker, Wolfgang, et al. “Scale4Edge – Scaling RISC-V for Edge Applications.” Scale4Edge – Scaling RISC-V for Edge Applications, 2023.
LibreCat | Files available
 
[17]
2021 | Conference Paper | LibreCat-ID: 32125
Adelt, Peer, et al. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, VDE, 2021.
LibreCat | Files available
 
[16]
2021 | Conference Paper | LibreCat-ID: 32132
Adelt, Peer, et al. “QEMU zur Simulation von Worst-Case-Ausführungszeiten.” MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, VDE, 2021.
LibreCat
 
[15]
2021 | Conference Paper | LibreCat-ID: 23992
Adelt, Peer, et al. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021), 2021.
LibreCat
 
[14]
2020 | Conference Paper | LibreCat-ID: 24027
Adelt, Peer, et al. “A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures.” MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, 2020.
LibreCat | Files available
 
[13]
2020 | Conference Paper | LibreCat-ID: 24023
Bahmanian, Meysam, et al. “Wide-Band Frequency Synthesizer with Ultra-Low Phase Noise Using an Optical Clock Source.” 2020 IEEE/MTT-S International Microwave Symposium (IMS), IEEE, 2020, doi:10.1109/IMS30576.2020.9224118.
LibreCat | Files available | DOI
 
[12]
2019 | Conference Paper | LibreCat-ID: 24058
Koppelmann, Bastian, et al. “RISC-V Extensions for Bit Manipulation Instructions.” 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2019, doi:10.1109/PATMOS.2019.8862170.
LibreCat | Files available | DOI
 
[11]
2019 | Conference Paper | LibreCat-ID: 24060
Adelt, Peer, et al. “Analyse Sicherheitskritischer Software Für RISC-V Prozessoren.” MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019), 2019.
LibreCat | Files available
 
[10]
2019 | Conference Paper | LibreCat-ID: 24061
Adelt, Peer, et al. “QEMU for Dynamic Memory Analysis of Security Sensitive Software.” 2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019, 2019, pp. 32–34.
LibreCat | Files available
 
[9]
2019 | Journal Article | LibreCat-ID: 24063
Adelt, Peer, et al. “QEMU Support for RISC-V: Current State and Future Releases.” 2nd International Workshop on RISC-V Research Activities, vol. (Presentation), 2019.
LibreCat | Files available
 
[8]
2018 | Journal Article | LibreCat-ID: 24194
Adelt, Peer, et al. “Current and Future RISC-V Activities for Virtual Prototyping and Chip Design.” International Workshop on RISC-V Research Activities, vol. Presentation, 2018.
LibreCat | Files available
 
[7]
2017 | Conference Paper | LibreCat-ID: 24220
Adelt, Peer, et al. “Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen.” Tagungsband des Wissenschaftsforums Intelligente Technische Systeme, Verlagsschriftenreihe des Heinz Nixdorf Instituts, 2017, doi:10.17619/UNIPB/1-93.
LibreCat | Files available | DOI
 
[6]
2017 | Conference Paper | LibreCat-ID: 24224
Adelt, Peer, et al. “ANALISA - A Tool for Static Instruction Set Analysis.” Design Automation and Testing in Europe (DATE), University Booth Interactive Presentation, 2017.
LibreCat | Files available
 
[5]
2017 | Conference Paper | LibreCat-ID: 24225
Adelt, Peer, et al. “An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries.” 2nd Workshop on Resiliency in Embedded Electronic Systems (REES) , 2017, p. 44.
LibreCat | Files available
 
[4]
2016 | Conference Paper | LibreCat-ID: 24264
Adelt, Peer, et al. “Fast Dynamic Fault Injection for Virtual Microcontroller Platforms.” Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC), 2016, doi:10.1109/VLSI-SoC.2016.7753545.
LibreCat | Files available | DOI
 
[3]
2014 | Conference Paper | LibreCat-ID: 25161
Koppelmann, Bastian, et al. “Portierung Der TriCore-Architektur Auf QEMU.” 17. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2014) , 2014.
LibreCat
 
[2]
2014 | Journal Article | LibreCat-ID: 24302
Koppelmann, Bastian, et al. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” Design and Verification Conference (DVCON EUROPE), 2014.
LibreCat | Files available
 
[1]
2014 | Conference Paper | LibreCat-ID: 34585
Koppelmann, Bastian, et al. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” Proceedings of the Design and Verification Conference Europe (DVCON Europe), 2014.
LibreCat
 

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18 Publications

Mark all

[18]
2023 | Conference Paper | LibreCat-ID: 45776
Ecker, Wolfgang, et al. “Scale4Edge – Scaling RISC-V for Edge Applications.” Scale4Edge – Scaling RISC-V for Edge Applications, 2023.
LibreCat | Files available
 
[17]
2021 | Conference Paper | LibreCat-ID: 32125
Adelt, Peer, et al. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, VDE, 2021.
LibreCat | Files available
 
[16]
2021 | Conference Paper | LibreCat-ID: 32132
Adelt, Peer, et al. “QEMU zur Simulation von Worst-Case-Ausführungszeiten.” MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, VDE, 2021.
LibreCat
 
[15]
2021 | Conference Paper | LibreCat-ID: 23992
Adelt, Peer, et al. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021), 2021.
LibreCat
 
[14]
2020 | Conference Paper | LibreCat-ID: 24027
Adelt, Peer, et al. “A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures.” MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, 2020.
LibreCat | Files available
 
[13]
2020 | Conference Paper | LibreCat-ID: 24023
Bahmanian, Meysam, et al. “Wide-Band Frequency Synthesizer with Ultra-Low Phase Noise Using an Optical Clock Source.” 2020 IEEE/MTT-S International Microwave Symposium (IMS), IEEE, 2020, doi:10.1109/IMS30576.2020.9224118.
LibreCat | Files available | DOI
 
[12]
2019 | Conference Paper | LibreCat-ID: 24058
Koppelmann, Bastian, et al. “RISC-V Extensions for Bit Manipulation Instructions.” 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2019, doi:10.1109/PATMOS.2019.8862170.
LibreCat | Files available | DOI
 
[11]
2019 | Conference Paper | LibreCat-ID: 24060
Adelt, Peer, et al. “Analyse Sicherheitskritischer Software Für RISC-V Prozessoren.” MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019), 2019.
LibreCat | Files available
 
[10]
2019 | Conference Paper | LibreCat-ID: 24061
Adelt, Peer, et al. “QEMU for Dynamic Memory Analysis of Security Sensitive Software.” 2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019, 2019, pp. 32–34.
LibreCat | Files available
 
[9]
2019 | Journal Article | LibreCat-ID: 24063
Adelt, Peer, et al. “QEMU Support for RISC-V: Current State and Future Releases.” 2nd International Workshop on RISC-V Research Activities, vol. (Presentation), 2019.
LibreCat | Files available
 
[8]
2018 | Journal Article | LibreCat-ID: 24194
Adelt, Peer, et al. “Current and Future RISC-V Activities for Virtual Prototyping and Chip Design.” International Workshop on RISC-V Research Activities, vol. Presentation, 2018.
LibreCat | Files available
 
[7]
2017 | Conference Paper | LibreCat-ID: 24220
Adelt, Peer, et al. “Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen.” Tagungsband des Wissenschaftsforums Intelligente Technische Systeme, Verlagsschriftenreihe des Heinz Nixdorf Instituts, 2017, doi:10.17619/UNIPB/1-93.
LibreCat | Files available | DOI
 
[6]
2017 | Conference Paper | LibreCat-ID: 24224
Adelt, Peer, et al. “ANALISA - A Tool for Static Instruction Set Analysis.” Design Automation and Testing in Europe (DATE), University Booth Interactive Presentation, 2017.
LibreCat | Files available
 
[5]
2017 | Conference Paper | LibreCat-ID: 24225
Adelt, Peer, et al. “An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries.” 2nd Workshop on Resiliency in Embedded Electronic Systems (REES) , 2017, p. 44.
LibreCat | Files available
 
[4]
2016 | Conference Paper | LibreCat-ID: 24264
Adelt, Peer, et al. “Fast Dynamic Fault Injection for Virtual Microcontroller Platforms.” Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC), 2016, doi:10.1109/VLSI-SoC.2016.7753545.
LibreCat | Files available | DOI
 
[3]
2014 | Conference Paper | LibreCat-ID: 25161
Koppelmann, Bastian, et al. “Portierung Der TriCore-Architektur Auf QEMU.” 17. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2014) , 2014.
LibreCat
 
[2]
2014 | Journal Article | LibreCat-ID: 24302
Koppelmann, Bastian, et al. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” Design and Verification Conference (DVCON EUROPE), 2014.
LibreCat | Files available
 
[1]
2014 | Conference Paper | LibreCat-ID: 34585
Koppelmann, Bastian, et al. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” Proceedings of the Design and Verification Conference Europe (DVCON Europe), 2014.
LibreCat
 

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