Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
P. Oehler, S. Hellebrand, H.-J. Wunderlich, in: 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), IEEE, Krakow, Poland, 2007, pp. 185–190.
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Author
Oehler, Philipp;
Hellebrand, SybilleLibreCat 
;
Wunderlich, Hans-Joachim
;
Wunderlich, Hans-JoachimDepartment
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Proceedings Title
10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'07)
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185-190
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Oehler P, Hellebrand S, Wunderlich H-J. Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. In: 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07). IEEE; 2007:185-190. doi:10.1109/ddecs.2007.4295278
Oehler, P., Hellebrand, S., & Wunderlich, H.-J. (2007). Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), 185–190. https://doi.org/10.1109/ddecs.2007.4295278
@inproceedings{Oehler_Hellebrand_Wunderlich_2007, place={Krakow, Poland}, title={Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair}, DOI={10.1109/ddecs.2007.4295278}, booktitle={10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07)}, publisher={IEEE}, author={Oehler, Philipp and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2007}, pages={185–190} }
Oehler, Philipp, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair.” In 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), 185–90. Krakow, Poland: IEEE, 2007. https://doi.org/10.1109/ddecs.2007.4295278.
P. Oehler, S. Hellebrand, and H.-J. Wunderlich, “Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair,” in 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), 2007, pp. 185–190, doi: 10.1109/ddecs.2007.4295278.
Oehler, Philipp, et al. “Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair.” 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), IEEE, 2007, pp. 185–90, doi:10.1109/ddecs.2007.4295278.
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