133 Publications

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[133]
2019 | Journal Article | LibreCat-ID: 8667
Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test
A. Sprenger, S. Hellebrand, Journal of Circuits, Systems and Computers (2019).
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[132]
2019 | Misc | LibreCat-ID: 8112
A Hybrid Space Compactor for Varying X-Rates
M.U. Maaz, A. Sprenger, S. Hellebrand, A Hybrid Space Compactor for Varying X-Rates, 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19), Prien am Chiemsee, 2019.
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[131]
2019 | Conference Paper | LibreCat-ID: 12918
A Hybrid Space Compactor for Adaptive X-Handling
M.U. Maaz, A. Sprenger, S. Hellebrand, in: 50th IEEE International Test Conference (ITC), IEEE, Washington, DC, USA, 2019, pp. 1–8.
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[130]
2019 | Journal Article | LibreCat-ID: 13048
Built-in Test for Hidden Delay Faults
M. Kampmann, M. A. Kochte, C. Liu, E. Schneider, S. Hellebrand, H.-J. Wunderlich, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 38 (2019) 1956–1968.
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[129]
2018 | Misc | LibreCat-ID: 4576
Stochastische Kompaktierung für den Hochgeschwindigkeitstest
A. Sprenger, S. Hellebrand, Stochastische Kompaktierung für den Hochgeschwindigkeitstest, 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), Freiburg, Germany, 2018.
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[128]
2018 | Journal Article | LibreCat-ID: 13057
Design For Small Delay Test - A Simulation Study
M. Kampmann, S. Hellebrand, Microelectronics Reliability 80 (2018) 124–133.
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[127]
2018 | Journal Article | LibreCat-ID: 12974
Guest Editors' Introduction - Special Issue on Approximate Computing
S. Hellebrand, J. Henkel, A. Raghunathan, H.-J. Wunderlich, IEEE Embedded Systems Letters 10 (2018) 1–1.
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[126]
2018 | Conference Paper | LibreCat-ID: 10575
Extending Aging Monitors for Early Life and Wear-Out Failure Prevention
C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, H.-J. Wunderlich, in: 2018 IEEE 27th Asian Test Symposium (ATS), 2018.
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[125]
2018 | Conference Paper | LibreCat-ID: 4575
Tuning Stochastic Space Compaction to Faster-than-at-Speed Test
A. Sprenger, S. Hellebrand, in: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, Budapest, 2018.
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[124]
2017 | Conference Paper | LibreCat-ID: 10576
Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test
M. Kampmann, S. Hellebrand, in: 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, 2017.
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[123]
2017 | Conference Paper | LibreCat-ID: 12973
Special Session on Early Life Failures
J. Deshmukh, W. Kunz, H.-J. Wunderlich, S. Hellebrand, in: 35th IEEE VLSI Test Symposium (VTS’17), IEEE, Caesars Palace, Las Vegas, Nevada, USA, 2017.
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[122]
2017 | Misc | LibreCat-ID: 13078
X-tolerante Prüfzellengruppierung für den Test mit erhöhter Betriebsfrequenz
M. Kampmann, S. Hellebrand, X-Tolerante Prüfzellengruppierung Für Den Test Mit Erhöhter Betriebsfrequenz, 29. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’17), Lübeck, Germany, 2017.
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[121]
2016 | Conference Paper | LibreCat-ID: 12975
X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test
M. Kampmann, S. Hellebrand, in: 25th IEEE Asian Test Symposium (ATS’16), IEEE, Hiroshima, Japan, 2016, pp. 1–6.
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[120]
2015 | Conference Paper | LibreCat-ID: 12976
Optimized Selection of Frequencies for Faster-Than-at-Speed Test
M. Kampmann, M. A. Kochte, E. Schneider, T. Indlekofer, S. Hellebrand, H.-J. Wunderlich, in: 24th IEEE Asian Test Symposium (ATS’15), IEEE, Mumbai, India, 2015, pp. 109–114.
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[119]
2015 | Journal Article | LibreCat-ID: 13056
A High Performance SEU Tolerant Latch
Z. Huang, H. Liang, S. Hellebrand, Journal of Electronic Testing - Theory and Applications (JETTA) 31 (2015) 349–359.
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[118]
2015 | Misc | LibreCat-ID: 13077
Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler
S. Hellebrand, T. Indlekofer, M. Kampmann, M. Kochte, C. Liu, H.-J. Wunderlich, Effiziente Auswahl von Testfrequenzen Für Den Test Kleiner Verzögerungsfehler, 27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany, 2015.
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[117]
2014 | Conference Paper | LibreCat-ID: 12977
FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects
S. Hellebrand, T. Indlekofer, M. Kampmann, M. A. Kochte, C. Liu, H.-J. Wunderlich, in: IEEE International Test Conference (ITC’14), IEEE, Seattle, Washington, USA, 2014.
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[116]
2014 | Journal Article | LibreCat-ID: 13054
SAT-Based ATPG beyond Stuck-at Fault Testing
S. Hellebrand, H.-J. Wunderlich, DeGruyter Journal on Information Technology (It) 56 (2014) 165–172.
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[115]
2014 | Journal Article | LibreCat-ID: 13055
Adaptive Bayesian Diagnosis of Intermittent Faults
L. Rodriguez Gomez, A. Cook, T. Indlekofer, S. Hellebrand, H.-J. Wunderlich, Journal of Electronic Testing - Theory and Applications (JETTA) 30 (2014) 527–540.
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[114]
2013 | Misc | LibreCat-ID: 13075
Adaptive Test and Diagnosis of Intermittent Faults
A. Cook, L. Rodriguez Gomez, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich, Adaptive Test and Diagnosis of Intermittent Faults, 14th Latin American Test Workshop, Cordoba, Argentina, 2013.
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[113]
2013 | Conference Paper | LibreCat-ID: 12979
Analyzing and Quantifying Fault Tolerance Properties
S. Hellebrand, in: 14th IEEE Latin American Test Workshop - (LATW’13), IEEE, Cordoba, Argentina, 2013.
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[112]
2012 | Conference Paper | LibreCat-ID: 12980
Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test
A. Cook, S. Hellebrand, M. E. Imhof, A. Mumtaz, H.-J. Wunderlich, in: 13th IEEE Latin American Test Workshop (LATW’12), IEEE, Quito, Ecuador, 2012, pp. 1–4.
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[111]
2012 | Conference Paper | LibreCat-ID: 12981
Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test
A. Cook, S. Hellebrand, H.-J. Wunderlich, in: 17th IEEE European Test Symposium (ETS’12), IEEE, Annecy, France, 2012, pp. 1–6.
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[110]
2012 | Misc | LibreCat-ID: 13074
Eingebaute Selbstdiagnose mit zufälligen und deterministischen Mustern
A. Cook, S. Hellebrand, H.-J. Wunderlich, Eingebaute Selbstdiagnose Mit Zufälligen Und Deterministischen Mustern, 24. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’12), Cottbus, Germany, 2012.
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[109]
2011 | Journal Article | LibreCat-ID: 13052
Variation-Aware Fault Modeling
F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, {SCIENCE CHINA Information Sciences, Science China Press, Co-Published with Springer} 54 (2011) 1813–1826.
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[108]
2011 | Conference Paper | LibreCat-ID: 12984
Towards Variation-Aware Test Methods
I. Polian, B. Becker, S. Hellebrand, H.-J. Wunderlich, P. Maxwell, in: 16th IEEE European Test Symposium Trondheim (ETS’11), IEEE, Trondheim, Norway, 2011.
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[107]
2011 | Conference Paper | LibreCat-ID: 13053
Robuster Selbsttest mit Diagnose
A. Cook, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich, in: 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit Und Entwurf,” Hamburg, Germany, 2011, pp. 48–53.
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[106]
2011 | Conference Paper | LibreCat-ID: 12982
Diagnostic Test of Robust Circuits
A. Cook, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich, in: 20th IEEE Asian Test Symposium (ATS’11), IEEE, New Delhi, India, 2011, pp. 285–290.
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[105]
2010 | Conference Paper | LibreCat-ID: 12983
Variation-Aware Fault Modeling
F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: {19th IEEE Asian Test Symposium (ATS’10)}, {IEEE}, Shanghai, China, 2010, pp. 87–93.
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[104]
2010 | Conference Paper | LibreCat-ID: 12988
Reusing NoC-Infrastructure for Test Data Compression
V. Froese, R. Ibers, S. Hellebrand, in: {28th IEEE VLSI Test Symposium (VTS’10)}, {IEEE}, Santa Cruz, CA, USA, 2010, pp. 227–231.
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[103]
2010 | Conference Paper | LibreCat-ID: 13049
Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits
B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: {4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper)}, Chicago, IL, USA, 2010.
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[102]
2010 | Conference Paper | LibreCat-ID: 13051
Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz
M. Hunger, S. Hellebrand, in: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Wildbad Kreuth, Germany, 2010, pp. 81–88.
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[101]
2010 | Conference Paper | LibreCat-ID: 12985
Efficient Test Response Compaction for Robust BIST Using Parity Sequences
T. Indlekofer, M. Schnittger, S. Hellebrand, in: {28th IEEE International Conference on Computer Design (ICCD’10)}, {IEEE}, Amsterdam, The Netherlands, 2010, pp. 480–485.
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[100]
2010 | Conference Paper | LibreCat-ID: 12986
The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems
M. Hunger, S. Hellebrand, in: {25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10)}, {IEEE}, Kyoto, Japan, 2010, pp. 101–108.
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[99]
2010 | Misc | LibreCat-ID: 10670
Testdatenkompression mit Hilfe der Netzwerkinfrastruktur
V. Fröse, R. Ibers, S. Hellebrand, Testdatenkompression Mit Hilfe Der Netzwerkinfrastruktur, 22. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany, 2010.
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[98]
2010 | Misc | LibreCat-ID: 13073
Nano-Electronic Systems
S. Hellebrand, Nano-Electronic Systems, Editorial, it 4/2010, pp. 179-180, 2010.
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[97]
2010 | Conference Paper | LibreCat-ID: 13050
Robuster Selbsttest mit extremer Kompaktierung
T. Indlekofer, M. Schnittger, S. Hellebrand, in: {4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf”}, Wildbad Kreuth, Germany, 2010, pp. 17–24.
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[96]
2010 | Conference Paper | LibreCat-ID: 12987
Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits
B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10), IEEE, Chicago, IL, USA, 2010.
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[95]
2009 | Conference Paper | LibreCat-ID: 12990
Are Robust Circuits Really Robust?
S. Hellebrand, M. Hunger, in: {24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk)}, {IEEE}, Chicago, IL, USA, 2009, p. 77.
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[94]
2009 | Conference Paper | LibreCat-ID: 12991
ATPG-Based Grading of Strong Fault-Secureness
M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, in: {15th IEEE International On-Line Testing Symposium (IOLTS’09)}, {IEEE}, Sesimbra-Lisbon, Portugal, 2009.
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[93]
2009 | Conference Paper | LibreCat-ID: 13030
Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung
M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, in: {3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf”}, Stuttgart, Germany, 2009.
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[92]
2008 | Conference Paper | LibreCat-ID: 13032
Modularer Selbsttest und optimierte Reparaturanalyse
P. Oehler, A. Bosio, G. Di Natale, S. Hellebrand, in: {2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf”}, Ingolstadt, Germany, 2008.
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[91]
2008 | Misc | LibreCat-ID: 13033
Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit
T. Coym, S. Hellebrand, S. Ludwig, B. Straube, H.-J. Wunderlich, C. G. Zoellin, Ein Verfeinertes Elektrisches Modell Für Teilchentreffer Und Dessen Auswirkung Auf Die Bewertung Der Schaltungsempfindlichkeit, 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich, 2008.
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[90]
2008 | Conference Paper | LibreCat-ID: 12992
A Modular Memory BIST for Optimized Memory Repair
P. Oehler, A. Bosio, G. di Natale, S. Hellebrand, in: {14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster)}, {IEEE}, Rhodos, Greece, 2008.
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[89]
2008 | Conference Paper | LibreCat-ID: 12993
Verification and Analysis of Self-Checking Properties through ATPG
M. Hunger, S. Hellebrand, in: {14th IEEE International On-Line Testing Symposium (IOLTS’08)}, {IEEE}, Rhodos, Greece, 2008.
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[88]
2008 | Misc | LibreCat-ID: 13035
Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen
U. Amgalan, C. Hachmann, S. Hellebrand, H.-J. Wunderlich, Testen Mit Rücksetzpunkten - Ein Ansatz Zur Verbesserung Der Ausbeute Bei Robusten Schaltungen, 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich, 2008.
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[87]
2008 | Conference Paper | LibreCat-ID: 12994
Signature Rollback - A Technique for Testing Robust Circuits
U. Amgalan, C. Hachmann, S. Hellebrand, H.-J. Wunderlich, in: {26th IEEE VLSI Test Symposium (VTS’08)}, {IEEE}, San Diego, CA, USA, 2008, pp. 125–130.
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[86]
2008 | Conference Paper | LibreCat-ID: 13031
Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG
M. Hunger, S. Hellebrand, in: {2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf”}, Ingolstadt, Germany, 2008.
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[85]
2007 | Conference Paper | LibreCat-ID: 12995
A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube, in: {22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07)}, {IEEE}, Rome, Italy, 2007, pp. 50–58.
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[84]
2007 | Conference Paper | LibreCat-ID: 13037
Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube, in: {43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper)}, Bled, Slovenia, 2007.
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[83]
2007 | Journal Article | LibreCat-ID: 13044
An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip
M. Ali, S. Hessler, M. Welzl, S. Hellebrand, {International Journal on High Performance Systems Architecture} 1 (2007) 113–123.
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[82]
2007 | Conference Paper | LibreCat-ID: 12996
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
P. Oehler, S. Hellebrand, H.-J. Wunderlich, in: {10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07)}, {IEEE}, Krakow, Poland, 2007, pp. 185–190.
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[81]
2007 | Conference Paper | LibreCat-ID: 13040
A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip
M. Ali, M. Welzl, S. Hessler, S. Hellebrand, in: {4th International Conference on Information Technology: New Generations (ITNG’07)}, Las Vegas, Nevada, USA, 2007, pp. 1027–1032.
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[80]
2007 | Misc | LibreCat-ID: 13038
Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing
S. Hellebrand, Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing, 5th IEEE East-West Design \& Test Symposium, Yerevan, Armenia (Invited Talk), 2007.
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[79]
2007 | Conference Paper | LibreCat-ID: 12997
An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy
P. Oehler, S. Hellebrand, H.-J. Wunderlich, in: {12th IEEE European Test Symposium (ETS’07)}, {IEEE}, Freiburg, Germany, 2007, pp. 91–96.
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[78]
2007 | Conference Paper | LibreCat-ID: 13041
Test und Zuverlässigkeit nanoelektronischer Systeme
B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich, in: {1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf”}, Munich, Germany, 2007.
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[77]
2007 | Misc | LibreCat-ID: 13039
An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips
M. Ali, M. Welzl, S. Hessler, S. Hellebrand, An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips, DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster), 2007.
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[76]
2007 | Misc | LibreCat-ID: 13042
An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy
P. Oehler, S. Hellebrand, H.-J. Wunderlich, An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy, 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany, 2007.
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[75]
2007 | Journal Article | LibreCat-ID: 13036
Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube, {Informacije MIDEM, Ljubljana (Invited Paper)} 37 (2007) 212–219.
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[74]
2007 | Misc | LibreCat-ID: 13043
Qualitätssicherung für Nanochips - Wie IT-Produkte zuverlässig werden
S. Hellebrand, Qualitätssicherung Für Nanochips - Wie IT-Produkte Zuverlässig Werden, ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany, 2007.
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[73]
2006 | Journal Article | LibreCat-ID: 13045
DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme
B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich, {it -Information Technology} 48 (2006) 305–311.
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[72]
2005 | Misc | LibreCat-ID: 13102
Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study
P. Oehler, S. Hellebrand, Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study, 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.
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[71]
2005 | Conference Paper | LibreCat-ID: 12998
A Dynamic Routing Mechanism for Network on Chip
M. Ali, M. Welzl, S. Hellebrand, in: {23rd IEEE NORCHIP Conference}, {IEEE}, Oulu, Finland, 2005, pp. 70–73.
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[70]
2005 | Conference Paper | LibreCat-ID: 13000
Low Power Embedded DRAMs with High Quality Error Correcting Capabilities
P. Oehler, S. Hellebrand, in: {10th IEEE European Test Symposium (ETS’05)}, {IEEE}, Tallinn, Estonia, 2005, pp. 148–153.
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[69]
2005 | Conference Paper | LibreCat-ID: 12999
Considerations for Fault-Tolerant Networks on Chips
M. Ali, M. Welzl, M. Zwicknagl, S. Hellebrand, in: {IEEE International Conference on Microelectronics (ICM’05)}, {IEEE}, Islamabad, Pakistan, 2005.
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[68]
2005 | Misc | LibreCat-ID: 13101
Dynamic Routing: A Prerequisite for Reliable NoCs
M. Ali, M. Welzl, S. Hellebrand, Dynamic Routing: A Prerequisite for Reliable NoCs, 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.
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[67]
2004 | Conference Paper | LibreCat-ID: 13001
Data Compression for Multiple Scan Chains Using Dictionaries with Corrections
A. Wuertenberger, C. S. Tautermann, S. Hellebrand, in: {IEEE International Test Conference (ITC’04)}, {IEEE}, Charlotte, NC, USA, 2004, pp. 926–935.
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[66]
2004 | Misc | LibreCat-ID: 13099
Im Westen viel Neues - Informatik an der Universität Innsbruck
R. Breu, T. Fahringer, D. Fensel, S. Hellebrand, A. Middeldorp, O. Scherzer, Im Westen Viel Neues - Informatik an Der Universität Innsbruck, OCG Journal, pp. 28-29, 2004.
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[65]
2004 | Misc | LibreCat-ID: 13100
Data Compression for Multiple Scan Chains Using Dictionaries with Corrections
S. Hellebrand, A. Wuertenberger, C. S. Tautermann, Data Compression for Multiple Scan Chains Using Dictionaries with Corrections, 9th IEEE European Test Symposium, Ajaccio, Corsica, France, 2004.
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[64]
2003 | Conference Paper | LibreCat-ID: 13002
A Hybrid Coding Strategy for Optimized Test Data Compression
A. Wuertenberger, C. S. Tautermann, S. Hellebrand, in: {IEEE International Test Conference (ITC’03)}, {IEEE}, Charlotte, NC, USA, 2003, pp. 451–459.
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[63]
2003 | Misc | LibreCat-ID: 13098
Experiences from Teaching Software Development in a Java Environment
R. Breu, S. Hellebrand, M. Welzl, Experiences from Teaching Software Development in a Java Environment, Handouts ACS/IEEE Workshop on Practice and Experience with Java in Education, Tunis, Tunisia, 2003.
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[62]
2002 | Journal Article | LibreCat-ID: 13070
A Mixed-Mode BIST Scheme Based on Folding Compression
H. Liang, S. Hellebrand, H.-J. Wunderlich, {Journal on Computer Science and Technology} 17 (2002) 203–212.
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[61]
2002 | Journal Article | LibreCat-ID: 13069
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
S. Hellebrand, H.-G. Liang, H.-J. Wunderlich, {Journal of Electronic Testing - Theory and Applications (JETTA)} 18 (2002) 157–168.
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[60]
2002 | Journal Article | LibreCat-ID: 13003
Efficient Online and Offline Testing of Embedded DRAMs
S. Hellebrand, H.-J. Wunderlich, A. A. Ivaniuk, Y. V. Klimets, V. N. Yarmolik, {IEEE Transactions on Computers} 51 (2002) 801–809.
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[59]
2002 | Misc | LibreCat-ID: 13097
Alternating Run-Length Coding: A Technique for Improved Test Data Compression
S. Hellebrand, A. Wuertenberger, Alternating Run-Length Coding: A Technique for Improved Test Data Compression, IEEE International Workshop on Test Resource Partitioning, Baltimore, MD, USA, 2002.
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[58]
2001 | Journal Article | LibreCat-ID: 13068
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
S. Hellebrand, H.-G. Liang, H.-J. Wunderlich, {Journal of Electronic Testing - Theory and Applications (JETTA)} 17 (2001) 341–349.
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[57]
2001 | Misc | LibreCat-ID: 13096
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
H.-G. Liang, S. Hellebrand, H.-J. Wunderlich, Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST, IEEE European Test Workshop, Stockholm, Sweden, 2001.
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[56]
2001 | Conference Paper | LibreCat-ID: 13004
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
H.-G. Liang, S. Hellebrand, H.-J. Wunderlich, in: {IEEE International Test Conference (ITC’01)}, {IEEE}, Baltimore, MD, USA, 2001, pp. 894–902.
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[55]
2001 | Journal Article | LibreCat-ID: 13047
Deterministic BIST Scheme Based on Reseeding of Folding Counters
H.-G. Liang, S. Hellebrand, H.-J. Wunderlich, {Journal of Computer Research and Development, (Jisuanji Yanjiu Yu Fazhan)} 38 (2001) 931.
LibreCat
 
[54]
2000 | Misc | LibreCat-ID: 13094
Hardwarepraktikum im Diplomstudiengang Informatik
S. Hellebrand, H.-J. Wunderlich, Hardwarepraktikum Im Diplomstudiengang Informatik, Handbuch Lehre, Berlin, Raabe Verlag, 2000.
LibreCat
 
[53]
2000 | Misc | LibreCat-ID: 13095
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
S. Hellebrand, H.-G. Liang, H.-J. Wunderlich, A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters, IEEE European Test Workshop, Cascais, Portugal, 2000.
LibreCat
 
[52]
2000 | Conference Paper | LibreCat-ID: 13005
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
S. Hellebrand, H.-G. Liang, H.-J. Wunderlich, in: {IEEE International Test Conference (ITC’00)}, {IEEE}, Atlantic City, NJ, USA, 2000, pp. 778–784.
LibreCat | DOI
 
[51]
1999 | Conference Paper | LibreCat-ID: 13006
Error Detecting Refreshment for Embedded DRAMs
S. Hellebrand, H.-J. Wunderlich, A. A. Ivaniuk, Y. V. Klimets, V. N. Yarmolik, in: {17th IEEE VLSI Test Symposium (VTS’99)}, {IEEE (Comput. Soc.)}, Dana Point, CA, USA, 1999, pp. 384–390.
LibreCat | DOI
 
[50]
1999 | Book | LibreCat-ID: 13065
Selbsttestbare Steuerwerke - Strukturen und Syntheseverfahren
S. Hellebrand, Selbsttestbare Steuerwerke - Strukturen Und Syntheseverfahren, Verlag Dr. Kovac, Hamburg, Verlag Dr. Kovac, Hamburg, 1999.
LibreCat
 
[49]
1999 | Conference Paper | LibreCat-ID: 13066
Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms
V. N. Yarmolik, I. V. Bykov, S. Hellebrand, H.-J. Wunderlich, in: {Third European Dependable Computing Conference (EDCC-3)}, Prague, Czech Republic, 1999.
LibreCat
 
[48]
1999 | Conference Paper | LibreCat-ID: 13067
Symmetric Transparent BIST for RAMs
S. Hellebrand, H.-J. Wunderlich, V. N. Yarmolik, in: {Design, Automation and Test in Europe (DATE’99)}, Munich, Germany, 1999, pp. 702–707.
LibreCat
 
[47]
1999 | Misc | LibreCat-ID: 13093
Exploiting Symmetries to Speed Up Transparent BIST
S. Hellebrand, H.-J. Wunderlich, V. N. Yarmolik, Exploiting Symmetries to Speed Up Transparent BIST, 11th GI/ITG/GMM/IEEE Workshop, 1999.
LibreCat
 
[46]
1998 | Conference Paper | LibreCat-ID: 13063
New Transparent RAM BIST Based on Self-Adjusting Output Data Compression
V. N. Yarmolik, Y. V. Klimets, S. Hellebrand, H.-J. Wunderlich, in: {Design \& Diagnostics of Electronic Circuits \& Systems}, Szczyrk, Poland, 1998, pp. 27–33.
LibreCat
 
[45]
1998 | Conference Paper | LibreCat-ID: 13007
Fast Self-Recovering Controllers
A. Hertwig, S. Hellebrand, H.-J. Wunderlich, in: {16th IEEE VLSI Test Symposium (VTS’98)}, {IEEE (Comput. Soc.)}, Monterey, CA, USA, 1998, pp. 296–302.
LibreCat | DOI
 
[44]
1998 | Journal Article | LibreCat-ID: 13064
Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications
S. Hellebrand, A. Hertwig, H.-J. Wunderlich, {IEEE Design and Test} 15 (1998) 36–41.
LibreCat
 
[43]
1998 | Conference Paper | LibreCat-ID: 13008
Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs
S. Hellebrand, H.-J. Wunderlich, V. N. Yarmolik, in: {IEEE Design, Automation and Test in Europe (DATE’98)}, {IEEE (Comput.Soc)}, Paris, France, 1998, pp. 173–179.
LibreCat | DOI
 
[42]
1998 | Book Chapter | LibreCat-ID: 13060
Mixed-Mode BIST Using Embedded Processors
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, in: Mixed-Mode BIST Using Embedded Processors, {Kluwer Academic Publishers}, In: M. Nicolaidis, Y. Zorian, D. K. Pradhan (Eds.): On-Line Testing for VLSI, Boston: Kluwer Academic Publishers 1998, 1998.
LibreCat
 
[41]
1998 | Misc | LibreCat-ID: 13091
Efficient Consistency Checking for Embedded Memories
V. N. Yarmolik, S. Hellebrand, H.-J. Wunderlich, Efficient Consistency Checking for Embedded Memories, 5th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1998.
LibreCat
 
[40]
1998 | Journal Article | LibreCat-ID: 13061
Mixed-Mode BIST Using Embedded Processors
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, {Journal of Electronic Testing Theory and Applications - JETTA} 12 (1998) 127–138.
LibreCat
 
[39]
1998 | Misc | LibreCat-ID: 13092
Efficient Consistency Checking for Embedded Memories
V. N. Yarmolik, S. Hellebrand, H.-J. Wunderlich, Efficient Consistency Checking for Embedded Memories, 10th GI/ITG/GMM/IEEE Workshop, 1998.
LibreCat
 
[38]
1998 | Report | LibreCat-ID: 13029
Test und Synthese schneller eingebetteter Systeme
S. Hellebrand, H.-J. Wunderlich, Test Und Synthese Schneller Eingebetteter Systeme, Universität Stuttgart, 1998.
LibreCat
 
[37]
1997 | Misc | LibreCat-ID: 13090
Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications
A. Hertwig, S. Hellebrand, H.-J. Wunderlich, Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications, 3rd IEEE International On-Line Testing Workshop, Crete, Greece, 1997.
LibreCat
 
[36]
1997 | Misc | LibreCat-ID: 13089
STARBIST: Scan Autocorrelated Random Pattern Generation
K.-H. Tsai, S. Hellebrand, J. Rajski, M. Marek-Sadowska, STARBIST: Scan Autocorrelated Random Pattern Generation, 4th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1997.
LibreCat
 
[35]
1997 | Conference Paper | LibreCat-ID: 13009
STARBIST: Scan Autocorrelated Random Pattern Generation
K.-H. Tsai, S. Hellebrand, M. Marek-Sadowska, J. Rajski, in: {34th ACM/IEEE Design Automation Conference (DAC’97)}, {IEEE}, Anaheim, CA, USA, 1997.
LibreCat | DOI
 
[34]
1996 | Misc | LibreCat-ID: 13087
Using Embedded Processors for BIST
S. Hellebrand, H.-J. Wunderlich, Using Embedded Processors for BIST, 3rd IEEE International Test Synthesis Workshop, Santa Barbara, CA, 1996.
LibreCat
 
[33]
1996 | Misc | LibreCat-ID: 13088
Mixed-Mode BIST Using Embedded Processors
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, Mixed-Mode BIST Using Embedded Processors, 2nd IEEE International On-Line Testing Workshop. Biarritz, France, 1996.
LibreCat
 
[32]
1996 | Conference Paper | LibreCat-ID: 13010
Mixed-Mode BIST Using Embedded Processors
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, in: {IEEE International Test Conference (ITC’96)}, {IEEE}, Washington, DC, USA, 1996, pp. 195–204.
LibreCat | DOI
 
[31]
1995 | Report | LibreCat-ID: 13026
Synthesis Procedures for Self-Testable Controllers
S. Hellebrand, H.-J. Wunderlich, Synthesis Procedures for Self-Testable Controllers, University of Siegen, Germany, 1995.
LibreCat
 
[30]
1995 | Report | LibreCat-ID: 13027
Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis
S. Hellebrand, H.-J. Wunderlich, F. Goncalves, J. Paulo Teixeira, Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis, University Siegen, Germany, 1995.
LibreCat
 
[29]
1995 | Journal Article | LibreCat-ID: 13011
Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers
S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, B. Courtois, {IEEE Transactions on Computers} 44 (1995) 223–233.
LibreCat | DOI
 
[28]
1995 | Report | LibreCat-ID: 13028
Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing
S. Hellebrand, M. Herzog, H.-J. Wunderlich, Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing, University of Siegen, Germany, 1995.
LibreCat
 
[27]
1995 | Conference Paper | LibreCat-ID: 13012
Pattern Generation for a Deterministic BIST Scheme
S. Hellebrand, B. Reeb, S. Tarnick, H.-J. Wunderlich, in: {ACM/IEEE International Conference on Computer Aided Design (ICCAD’95)}, {IEEE (Comput. Soc. Press)}, San Jose, CA, USA, 1995, pp. 88–94.
LibreCat | DOI
 
[26]
1995 | Misc | LibreCat-ID: 13086
Pattern Generation for a Deterministic BIST Scheme
S. Hellebrand, B. Reeb, S. Tarnick, H.-J. Wunderlich, Pattern Generation for a Deterministic BIST Scheme, 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA, 1995.
LibreCat
 
[25]
1994 | Conference Paper | LibreCat-ID: 13013
Synthesis of Self-Testable Controllers
S. Hellebrand, H.-J. Wunderlich, in: {European Design and Test Conference (EDAC/ETC/EUROASIC)}, {IEEE (Comput. Soc. Press)}, Paris, France, 1994, pp. 580–585.
LibreCat | DOI
 
[24]
1994 | Report | LibreCat-ID: 13025
Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time
S. Hellebrand, A. Juergensen, A. Stroele, H.-J. Wunderlich, Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time, University of Siegen, Germany, 1994.
LibreCat
 
[23]
1994 | Conference Paper | LibreCat-ID: 13014
An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures
S. Hellebrand, H.-J. Wunderlich, in: {ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94)}, {IEEE}, San Jose, CA, USA, 1994, pp. 110–116.
LibreCat | DOI
 
[22]
1994 | Misc | LibreCat-ID: 13083
Effiziente Testsatzkodierung für Prüfpfad-basierte Selbsttestarchitekturen
S. Venkataraman, J. Rajski, S. Hellebrand, S. Tarnick, Effiziente Testsatzkodierung Für Prüfpfad-Basierte Selbsttestarchitekturen, 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands, 1994.
LibreCat
 
[21]
1994 | Misc | LibreCat-ID: 13084
Ein Verfahren zur testfreundlichen Steuerwerkssynthese
S. Hellebrand, H.-J. Wunderlich, Ein Verfahren Zur Testfreundlichen Steuerwerkssynthese, 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands, 1994.
LibreCat
 
[20]
1994 | Conference Paper | LibreCat-ID: 13059
Synthese schneller selbsttestbarer Steuerwerke
S. Hellebrand, H.-J. Wunderlich, in: {Tagungsband Der GI/GME/ITG-Fachtagung \& Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme}, Oberwiesenthal, Informatik Xpress 4, TU Chemnitz Zwickau, Germany, 1994, pp. 3–11.
LibreCat
 
[19]
1994 | Misc | LibreCat-ID: 13085
Synthesis for Testability - the ARCHIMEDES Approach
S. Hellebrand, J. Paulo Teixeira, H.-J. Wunderlich, Synthesis for Testability - the ARCHIMEDES Approach, 1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1994.
LibreCat
 
[18]
1994 | Report | LibreCat-ID: 13024
Synthesis for Off-line Testability
S. Hellebrand, A. Juergensen, H.-J. Wunderlich, Synthesis for Off-Line Testability, University of Siegen, Germany, 1994.
LibreCat
 
[17]
1993 | Misc | LibreCat-ID: 13082
Synthesis of Self-Testable Controllers
S. Hellebrand, H.-J. Wunderlich, Synthesis of Self-Testable Controllers, ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support”, Montpellier, France, 1993.
LibreCat
 
[16]
1993 | Conference Paper | LibreCat-ID: 13015
An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers
S. Venkataraman, J. Rajski, S. Hellebrand, S. Tarnick, in: {ACM/IEEE International Conference on Computer Aided Design (ICCAD’93)}, {IEEE (Comput. Soc. Press)}, 1993.
LibreCat | DOI
 
[15]
1993 | Misc | LibreCat-ID: 13081
Effiziente Erzeugung deterministischer Muster im Selbsttest
S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, Effiziente Erzeugung Deterministischer Muster Im Selbsttest, 5th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Holzhau, Germany, 1993.
LibreCat
 
[14]
1992 | Misc | LibreCat-ID: 13076
Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs
S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs, IEEE Design for Testability Workshop, Vail, CO, USA, 1992.
LibreCat
 
[13]
1992 | Conference Paper | LibreCat-ID: 13016
Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers
S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, in: {IEEE International Test Conference (ITC’92)}, {IEEE}, Baltimore, MD, USA, 1992, pp. 120–129.
LibreCat | DOI
 
[12]
1992 | Report | LibreCat-ID: 13023
Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs
S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs, Institut National Polytechnique de Grenoble, Grenoble, France, 1992.
LibreCat
 
[11]
1992 | Misc | LibreCat-ID: 13080
Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs
S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs, Workshop on New Directions for Testing, Montreal, Canada, 1992.
LibreCat
 
[10]
1992 | Journal Article | LibreCat-ID: 13017
The Pseudoexhaustive Test of Sequential Circuits
H.-J. Wunderlich, S. Hellebrand, {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)} 11 (1992) 26–33.
LibreCat | DOI
 
[9]
1991 | Book | LibreCat-ID: 13034
Synthese vollständig testbarer Schaltungen
S. Hellebrand, Synthese Vollständig Testbarer Schaltungen, Verlag Düsseldorf: VDI Verlag, Verlag Düsseldorf: VDI Verlag, 1991.
LibreCat
 
[8]
1990 | Conference Paper | LibreCat-ID: 13018
Tools and Devices Supporting the Pseudo-Exhaustive Test
S. Hellebrand, H.-J. Wunderlich, in: {European Design Automation Conference (EDAC’90)}, {IEEE (Comput. Soc. Press)}, Glasgow, UK, 1990, pp. 13–17.
LibreCat | DOI
 
[7]
1990 | Conference Paper | LibreCat-ID: 13019
Generating Pseudo-Exhaustive Vectors for External Testing
S. Hellebrand, H.-J. Wunderlich, O. F. Haberl, in: {IEEE International Test Conference (ITC’90)}, {IEEE (Comput. Soc. Press)}, Washington, DC, USA, 1990, pp. 670–679.
LibreCat | DOI
 
[6]
1990 | Misc | LibreCat-ID: 13103
Generating Pseudo-Exhaustive Vectors for External Testing
S. Hellebrand, H.-J. Wunderlich, O. F. Haberl, Generating Pseudo-Exhaustive Vectors for External Testing, IEEE Design for Testability Workshop, Vail, CO, USA, 1990.
LibreCat
 
[5]
1989 | Conference Paper | LibreCat-ID: 13020
The Pseudo-Exhaustive Test of Sequential Circuits
H.-J. Wunderlich, S. Hellebrand, in: {IEEE International Test Conference (ITC’89)}, {IEEE (Comput. Soc. Press)}, Washington, DC, USA, 1989, pp. 19–27.
LibreCat | DOI
 
[4]
1988 | Conference Paper | LibreCat-ID: 13021
Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits
H.-J. Wunderlich, S. Hellebrand, in: {18th International Symposium on Fault-Tolerant Computing, FTCS-18}, {IEEE (Comput. Soc. Press)}, Tokyo, Japan, 1988, pp. 36–45.
LibreCat | DOI
 
[3]
1988 | Conference Paper | LibreCat-ID: 13058
Integrated Tools for Automatic Design for Testability
D. Schmid, H.-J. Wunderlich, F. Feldbusch, S. Hellebrand, J. Holzinger, A. Kunzmann, in: {In: Tool Integration and Design Environments, F.J. Rammig (Editor)}, Amsterdam: Elsevier Science Publishers B.V.(North Holland), IFIP, Amsterdam, The Netherlands, 1988, pp. 233–258.
LibreCat
 
[2]
1988 | Conference Paper | LibreCat-ID: 13062
Automatisierung des Entwurfs vollständig testbarer Schaltungen
S. Hellebrand, H.-J. Wunderlich, in: {GI - 18. Jahrestagung II, Hamburg, 1988, Informatik-Fachberichte 188}, Springer Verlag, Hamburg, Germany, 1988, pp. 145–159.
LibreCat
 
[1]
1986 | Report | LibreCat-ID: 13022
Deformation dicker Punkte und Netze von Quadriken
S. Hellebrand, Deformation Dicker Punkte Und Netze von Quadriken, Universität Regensburg, Fakultät für Mathematik, Regensburg, Germany, 1986.
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[133]
2019 | Journal Article | LibreCat-ID: 8667
Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test
A. Sprenger, S. Hellebrand, Journal of Circuits, Systems and Computers (2019).
LibreCat | DOI
 
[132]
2019 | Misc | LibreCat-ID: 8112
A Hybrid Space Compactor for Varying X-Rates
M.U. Maaz, A. Sprenger, S. Hellebrand, A Hybrid Space Compactor for Varying X-Rates, 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19), Prien am Chiemsee, 2019.
LibreCat
 
[131]
2019 | Conference Paper | LibreCat-ID: 12918
A Hybrid Space Compactor for Adaptive X-Handling
M.U. Maaz, A. Sprenger, S. Hellebrand, in: 50th IEEE International Test Conference (ITC), IEEE, Washington, DC, USA, 2019, pp. 1–8.
LibreCat
 
[130]
2019 | Journal Article | LibreCat-ID: 13048
Built-in Test for Hidden Delay Faults
M. Kampmann, M. A. Kochte, C. Liu, E. Schneider, S. Hellebrand, H.-J. Wunderlich, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 38 (2019) 1956–1968.
LibreCat
 
[129]
2018 | Misc | LibreCat-ID: 4576
Stochastische Kompaktierung für den Hochgeschwindigkeitstest
A. Sprenger, S. Hellebrand, Stochastische Kompaktierung für den Hochgeschwindigkeitstest, 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), Freiburg, Germany, 2018.
LibreCat
 
[128]
2018 | Journal Article | LibreCat-ID: 13057
Design For Small Delay Test - A Simulation Study
M. Kampmann, S. Hellebrand, Microelectronics Reliability 80 (2018) 124–133.
LibreCat
 
[127]
2018 | Journal Article | LibreCat-ID: 12974
Guest Editors' Introduction - Special Issue on Approximate Computing
S. Hellebrand, J. Henkel, A. Raghunathan, H.-J. Wunderlich, IEEE Embedded Systems Letters 10 (2018) 1–1.
LibreCat | DOI
 
[126]
2018 | Conference Paper | LibreCat-ID: 10575
Extending Aging Monitors for Early Life and Wear-Out Failure Prevention
C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, H.-J. Wunderlich, in: 2018 IEEE 27th Asian Test Symposium (ATS), 2018.
LibreCat | DOI
 
[125]
2018 | Conference Paper | LibreCat-ID: 4575
Tuning Stochastic Space Compaction to Faster-than-at-Speed Test
A. Sprenger, S. Hellebrand, in: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, Budapest, 2018.
LibreCat | DOI
 
[124]
2017 | Conference Paper | LibreCat-ID: 10576
Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test
M. Kampmann, S. Hellebrand, in: 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, 2017.
LibreCat | DOI
 
[123]
2017 | Conference Paper | LibreCat-ID: 12973
Special Session on Early Life Failures
J. Deshmukh, W. Kunz, H.-J. Wunderlich, S. Hellebrand, in: 35th IEEE VLSI Test Symposium (VTS’17), IEEE, Caesars Palace, Las Vegas, Nevada, USA, 2017.
LibreCat | DOI
 
[122]
2017 | Misc | LibreCat-ID: 13078
X-tolerante Prüfzellengruppierung für den Test mit erhöhter Betriebsfrequenz
M. Kampmann, S. Hellebrand, X-Tolerante Prüfzellengruppierung Für Den Test Mit Erhöhter Betriebsfrequenz, 29. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’17), Lübeck, Germany, 2017.
LibreCat
 
[121]
2016 | Conference Paper | LibreCat-ID: 12975
X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test
M. Kampmann, S. Hellebrand, in: 25th IEEE Asian Test Symposium (ATS’16), IEEE, Hiroshima, Japan, 2016, pp. 1–6.
LibreCat | DOI
 
[120]
2015 | Conference Paper | LibreCat-ID: 12976
Optimized Selection of Frequencies for Faster-Than-at-Speed Test
M. Kampmann, M. A. Kochte, E. Schneider, T. Indlekofer, S. Hellebrand, H.-J. Wunderlich, in: 24th IEEE Asian Test Symposium (ATS’15), IEEE, Mumbai, India, 2015, pp. 109–114.
LibreCat | DOI
 
[119]
2015 | Journal Article | LibreCat-ID: 13056
A High Performance SEU Tolerant Latch
Z. Huang, H. Liang, S. Hellebrand, Journal of Electronic Testing - Theory and Applications (JETTA) 31 (2015) 349–359.
LibreCat
 
[118]
2015 | Misc | LibreCat-ID: 13077
Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler
S. Hellebrand, T. Indlekofer, M. Kampmann, M. Kochte, C. Liu, H.-J. Wunderlich, Effiziente Auswahl von Testfrequenzen Für Den Test Kleiner Verzögerungsfehler, 27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany, 2015.
LibreCat
 
[117]
2014 | Conference Paper | LibreCat-ID: 12977
FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects
S. Hellebrand, T. Indlekofer, M. Kampmann, M. A. Kochte, C. Liu, H.-J. Wunderlich, in: IEEE International Test Conference (ITC’14), IEEE, Seattle, Washington, USA, 2014.
LibreCat | DOI
 
[116]
2014 | Journal Article | LibreCat-ID: 13054
SAT-Based ATPG beyond Stuck-at Fault Testing
S. Hellebrand, H.-J. Wunderlich, DeGruyter Journal on Information Technology (It) 56 (2014) 165–172.
LibreCat
 
[115]
2014 | Journal Article | LibreCat-ID: 13055
Adaptive Bayesian Diagnosis of Intermittent Faults
L. Rodriguez Gomez, A. Cook, T. Indlekofer, S. Hellebrand, H.-J. Wunderlich, Journal of Electronic Testing - Theory and Applications (JETTA) 30 (2014) 527–540.
LibreCat
 
[114]
2013 | Misc | LibreCat-ID: 13075
Adaptive Test and Diagnosis of Intermittent Faults
A. Cook, L. Rodriguez Gomez, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich, Adaptive Test and Diagnosis of Intermittent Faults, 14th Latin American Test Workshop, Cordoba, Argentina, 2013.
LibreCat
 
[113]
2013 | Conference Paper | LibreCat-ID: 12979
Analyzing and Quantifying Fault Tolerance Properties
S. Hellebrand, in: 14th IEEE Latin American Test Workshop - (LATW’13), IEEE, Cordoba, Argentina, 2013.
LibreCat | DOI
 
[112]
2012 | Conference Paper | LibreCat-ID: 12980
Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test
A. Cook, S. Hellebrand, M. E. Imhof, A. Mumtaz, H.-J. Wunderlich, in: 13th IEEE Latin American Test Workshop (LATW’12), IEEE, Quito, Ecuador, 2012, pp. 1–4.
LibreCat | DOI
 
[111]
2012 | Conference Paper | LibreCat-ID: 12981
Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test
A. Cook, S. Hellebrand, H.-J. Wunderlich, in: 17th IEEE European Test Symposium (ETS’12), IEEE, Annecy, France, 2012, pp. 1–6.
LibreCat | DOI
 
[110]
2012 | Misc | LibreCat-ID: 13074
Eingebaute Selbstdiagnose mit zufälligen und deterministischen Mustern
A. Cook, S. Hellebrand, H.-J. Wunderlich, Eingebaute Selbstdiagnose Mit Zufälligen Und Deterministischen Mustern, 24. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’12), Cottbus, Germany, 2012.
LibreCat
 
[109]
2011 | Journal Article | LibreCat-ID: 13052
Variation-Aware Fault Modeling
F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, {SCIENCE CHINA Information Sciences, Science China Press, Co-Published with Springer} 54 (2011) 1813–1826.
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[108]
2011 | Conference Paper | LibreCat-ID: 12984
Towards Variation-Aware Test Methods
I. Polian, B. Becker, S. Hellebrand, H.-J. Wunderlich, P. Maxwell, in: 16th IEEE European Test Symposium Trondheim (ETS’11), IEEE, Trondheim, Norway, 2011.
LibreCat | DOI
 
[107]
2011 | Conference Paper | LibreCat-ID: 13053
Robuster Selbsttest mit Diagnose
A. Cook, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich, in: 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit Und Entwurf,” Hamburg, Germany, 2011, pp. 48–53.
LibreCat
 
[106]
2011 | Conference Paper | LibreCat-ID: 12982
Diagnostic Test of Robust Circuits
A. Cook, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich, in: 20th IEEE Asian Test Symposium (ATS’11), IEEE, New Delhi, India, 2011, pp. 285–290.
LibreCat | DOI
 
[105]
2010 | Conference Paper | LibreCat-ID: 12983
Variation-Aware Fault Modeling
F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: {19th IEEE Asian Test Symposium (ATS’10)}, {IEEE}, Shanghai, China, 2010, pp. 87–93.
LibreCat | DOI
 
[104]
2010 | Conference Paper | LibreCat-ID: 12988
Reusing NoC-Infrastructure for Test Data Compression
V. Froese, R. Ibers, S. Hellebrand, in: {28th IEEE VLSI Test Symposium (VTS’10)}, {IEEE}, Santa Cruz, CA, USA, 2010, pp. 227–231.
LibreCat | DOI
 
[103]
2010 | Conference Paper | LibreCat-ID: 13049
Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits
B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: {4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper)}, Chicago, IL, USA, 2010.
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[102]
2010 | Conference Paper | LibreCat-ID: 13051
Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz
M. Hunger, S. Hellebrand, in: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Wildbad Kreuth, Germany, 2010, pp. 81–88.
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[101]
2010 | Conference Paper | LibreCat-ID: 12985
Efficient Test Response Compaction for Robust BIST Using Parity Sequences
T. Indlekofer, M. Schnittger, S. Hellebrand, in: {28th IEEE International Conference on Computer Design (ICCD’10)}, {IEEE}, Amsterdam, The Netherlands, 2010, pp. 480–485.
LibreCat | DOI
 
[100]
2010 | Conference Paper | LibreCat-ID: 12986
The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems
M. Hunger, S. Hellebrand, in: {25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10)}, {IEEE}, Kyoto, Japan, 2010, pp. 101–108.
LibreCat | DOI
 
[99]
2010 | Misc | LibreCat-ID: 10670
Testdatenkompression mit Hilfe der Netzwerkinfrastruktur
V. Fröse, R. Ibers, S. Hellebrand, Testdatenkompression Mit Hilfe Der Netzwerkinfrastruktur, 22. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany, 2010.
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[98]
2010 | Misc | LibreCat-ID: 13073
Nano-Electronic Systems
S. Hellebrand, Nano-Electronic Systems, Editorial, it 4/2010, pp. 179-180, 2010.
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[97]
2010 | Conference Paper | LibreCat-ID: 13050
Robuster Selbsttest mit extremer Kompaktierung
T. Indlekofer, M. Schnittger, S. Hellebrand, in: {4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf”}, Wildbad Kreuth, Germany, 2010, pp. 17–24.
LibreCat
 
[96]
2010 | Conference Paper | LibreCat-ID: 12987
Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits
B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10), IEEE, Chicago, IL, USA, 2010.
LibreCat | DOI
 
[95]
2009 | Conference Paper | LibreCat-ID: 12990
Are Robust Circuits Really Robust?
S. Hellebrand, M. Hunger, in: {24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk)}, {IEEE}, Chicago, IL, USA, 2009, p. 77.
LibreCat | DOI
 
[94]
2009 | Conference Paper | LibreCat-ID: 12991
ATPG-Based Grading of Strong Fault-Secureness
M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, in: {15th IEEE International On-Line Testing Symposium (IOLTS’09)}, {IEEE}, Sesimbra-Lisbon, Portugal, 2009.
LibreCat | DOI
 
[93]
2009 | Conference Paper | LibreCat-ID: 13030
Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung
M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, in: {3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf”}, Stuttgart, Germany, 2009.
LibreCat
 
[92]
2008 | Conference Paper | LibreCat-ID: 13032
Modularer Selbsttest und optimierte Reparaturanalyse
P. Oehler, A. Bosio, G. Di Natale, S. Hellebrand, in: {2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf”}, Ingolstadt, Germany, 2008.
LibreCat
 
[91]
2008 | Misc | LibreCat-ID: 13033
Ein verfeinertes elektrisches Modell für Teilchentreffer und dessen Auswirkung auf die Bewertung der Schaltungsempfindlichkeit
T. Coym, S. Hellebrand, S. Ludwig, B. Straube, H.-J. Wunderlich, C. G. Zoellin, Ein Verfeinertes Elektrisches Modell Für Teilchentreffer Und Dessen Auswirkung Auf Die Bewertung Der Schaltungsempfindlichkeit, 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich, 2008.
LibreCat
 
[90]
2008 | Conference Paper | LibreCat-ID: 12992
A Modular Memory BIST for Optimized Memory Repair
P. Oehler, A. Bosio, G. di Natale, S. Hellebrand, in: {14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster)}, {IEEE}, Rhodos, Greece, 2008.
LibreCat | DOI
 
[89]
2008 | Conference Paper | LibreCat-ID: 12993
Verification and Analysis of Self-Checking Properties through ATPG
M. Hunger, S. Hellebrand, in: {14th IEEE International On-Line Testing Symposium (IOLTS’08)}, {IEEE}, Rhodos, Greece, 2008.
LibreCat | DOI
 
[88]
2008 | Misc | LibreCat-ID: 13035
Testen mit Rücksetzpunkten - ein Ansatz zur Verbesserung der Ausbeute bei robusten Schaltungen
U. Amgalan, C. Hachmann, S. Hellebrand, H.-J. Wunderlich, Testen Mit Rücksetzpunkten - Ein Ansatz Zur Verbesserung Der Ausbeute Bei Robusten Schaltungen, 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich, 2008.
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[87]
2008 | Conference Paper | LibreCat-ID: 12994
Signature Rollback - A Technique for Testing Robust Circuits
U. Amgalan, C. Hachmann, S. Hellebrand, H.-J. Wunderlich, in: {26th IEEE VLSI Test Symposium (VTS’08)}, {IEEE}, San Diego, CA, USA, 2008, pp. 125–130.
LibreCat | DOI
 
[86]
2008 | Conference Paper | LibreCat-ID: 13031
Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG
M. Hunger, S. Hellebrand, in: {2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf”}, Ingolstadt, Germany, 2008.
LibreCat
 
[85]
2007 | Conference Paper | LibreCat-ID: 12995
A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube, in: {22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07)}, {IEEE}, Rome, Italy, 2007, pp. 50–58.
LibreCat | DOI
 
[84]
2007 | Conference Paper | LibreCat-ID: 13037
Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube, in: {43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper)}, Bled, Slovenia, 2007.
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[83]
2007 | Journal Article | LibreCat-ID: 13044
An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip
M. Ali, S. Hessler, M. Welzl, S. Hellebrand, {International Journal on High Performance Systems Architecture} 1 (2007) 113–123.
LibreCat
 
[82]
2007 | Conference Paper | LibreCat-ID: 12996
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
P. Oehler, S. Hellebrand, H.-J. Wunderlich, in: {10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07)}, {IEEE}, Krakow, Poland, 2007, pp. 185–190.
LibreCat | DOI
 
[81]
2007 | Conference Paper | LibreCat-ID: 13040
A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip
M. Ali, M. Welzl, S. Hessler, S. Hellebrand, in: {4th International Conference on Information Technology: New Generations (ITNG’07)}, Las Vegas, Nevada, USA, 2007, pp. 1027–1032.
LibreCat
 
[80]
2007 | Misc | LibreCat-ID: 13038
Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing
S. Hellebrand, Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing, 5th IEEE East-West Design \& Test Symposium, Yerevan, Armenia (Invited Talk), 2007.
LibreCat
 
[79]
2007 | Conference Paper | LibreCat-ID: 12997
An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy
P. Oehler, S. Hellebrand, H.-J. Wunderlich, in: {12th IEEE European Test Symposium (ETS’07)}, {IEEE}, Freiburg, Germany, 2007, pp. 91–96.
LibreCat | DOI
 
[78]
2007 | Conference Paper | LibreCat-ID: 13041
Test und Zuverlässigkeit nanoelektronischer Systeme
B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich, in: {1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf”}, Munich, Germany, 2007.
LibreCat
 
[77]
2007 | Misc | LibreCat-ID: 13039
An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips
M. Ali, M. Welzl, S. Hessler, S. Hellebrand, An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips, DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster), 2007.
LibreCat
 
[76]
2007 | Misc | LibreCat-ID: 13042
An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy
P. Oehler, S. Hellebrand, H.-J. Wunderlich, An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy, 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany, 2007.
LibreCat
 
[75]
2007 | Journal Article | LibreCat-ID: 13036
Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube, {Informacije MIDEM, Ljubljana (Invited Paper)} 37 (2007) 212–219.
LibreCat
 
[74]
2007 | Misc | LibreCat-ID: 13043
Qualitätssicherung für Nanochips - Wie IT-Produkte zuverlässig werden
S. Hellebrand, Qualitätssicherung Für Nanochips - Wie IT-Produkte Zuverlässig Werden, ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany, 2007.
LibreCat
 
[73]
2006 | Journal Article | LibreCat-ID: 13045
DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme
B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich, {it -Information Technology} 48 (2006) 305–311.
LibreCat
 
[72]
2005 | Misc | LibreCat-ID: 13102
Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study
P. Oehler, S. Hellebrand, Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study, 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.
LibreCat
 
[71]
2005 | Conference Paper | LibreCat-ID: 12998
A Dynamic Routing Mechanism for Network on Chip
M. Ali, M. Welzl, S. Hellebrand, in: {23rd IEEE NORCHIP Conference}, {IEEE}, Oulu, Finland, 2005, pp. 70–73.
LibreCat | DOI
 
[70]
2005 | Conference Paper | LibreCat-ID: 13000
Low Power Embedded DRAMs with High Quality Error Correcting Capabilities
P. Oehler, S. Hellebrand, in: {10th IEEE European Test Symposium (ETS’05)}, {IEEE}, Tallinn, Estonia, 2005, pp. 148–153.
LibreCat | DOI
 
[69]
2005 | Conference Paper | LibreCat-ID: 12999
Considerations for Fault-Tolerant Networks on Chips
M. Ali, M. Welzl, M. Zwicknagl, S. Hellebrand, in: {IEEE International Conference on Microelectronics (ICM’05)}, {IEEE}, Islamabad, Pakistan, 2005.
LibreCat | DOI
 
[68]
2005 | Misc | LibreCat-ID: 13101
Dynamic Routing: A Prerequisite for Reliable NoCs
M. Ali, M. Welzl, S. Hellebrand, Dynamic Routing: A Prerequisite for Reliable NoCs, 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.
LibreCat
 
[67]
2004 | Conference Paper | LibreCat-ID: 13001
Data Compression for Multiple Scan Chains Using Dictionaries with Corrections
A. Wuertenberger, C. S. Tautermann, S. Hellebrand, in: {IEEE International Test Conference (ITC’04)}, {IEEE}, Charlotte, NC, USA, 2004, pp. 926–935.
LibreCat | DOI
 
[66]
2004 | Misc | LibreCat-ID: 13099
Im Westen viel Neues - Informatik an der Universität Innsbruck
R. Breu, T. Fahringer, D. Fensel, S. Hellebrand, A. Middeldorp, O. Scherzer, Im Westen Viel Neues - Informatik an Der Universität Innsbruck, OCG Journal, pp. 28-29, 2004.
LibreCat
 
[65]
2004 | Misc | LibreCat-ID: 13100
Data Compression for Multiple Scan Chains Using Dictionaries with Corrections
S. Hellebrand, A. Wuertenberger, C. S. Tautermann, Data Compression for Multiple Scan Chains Using Dictionaries with Corrections, 9th IEEE European Test Symposium, Ajaccio, Corsica, France, 2004.
LibreCat
 
[64]
2003 | Conference Paper | LibreCat-ID: 13002
A Hybrid Coding Strategy for Optimized Test Data Compression
A. Wuertenberger, C. S. Tautermann, S. Hellebrand, in: {IEEE International Test Conference (ITC’03)}, {IEEE}, Charlotte, NC, USA, 2003, pp. 451–459.
LibreCat | DOI
 
[63]
2003 | Misc | LibreCat-ID: 13098
Experiences from Teaching Software Development in a Java Environment
R. Breu, S. Hellebrand, M. Welzl, Experiences from Teaching Software Development in a Java Environment, Handouts ACS/IEEE Workshop on Practice and Experience with Java in Education, Tunis, Tunisia, 2003.
LibreCat
 
[62]
2002 | Journal Article | LibreCat-ID: 13070
A Mixed-Mode BIST Scheme Based on Folding Compression
H. Liang, S. Hellebrand, H.-J. Wunderlich, {Journal on Computer Science and Technology} 17 (2002) 203–212.
LibreCat
 
[61]
2002 | Journal Article | LibreCat-ID: 13069
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
S. Hellebrand, H.-G. Liang, H.-J. Wunderlich, {Journal of Electronic Testing - Theory and Applications (JETTA)} 18 (2002) 157–168.
LibreCat
 
[60]
2002 | Journal Article | LibreCat-ID: 13003
Efficient Online and Offline Testing of Embedded DRAMs
S. Hellebrand, H.-J. Wunderlich, A. A. Ivaniuk, Y. V. Klimets, V. N. Yarmolik, {IEEE Transactions on Computers} 51 (2002) 801–809.
LibreCat | DOI
 
[59]
2002 | Misc | LibreCat-ID: 13097
Alternating Run-Length Coding: A Technique for Improved Test Data Compression
S. Hellebrand, A. Wuertenberger, Alternating Run-Length Coding: A Technique for Improved Test Data Compression, IEEE International Workshop on Test Resource Partitioning, Baltimore, MD, USA, 2002.
LibreCat
 
[58]
2001 | Journal Article | LibreCat-ID: 13068
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
S. Hellebrand, H.-G. Liang, H.-J. Wunderlich, {Journal of Electronic Testing - Theory and Applications (JETTA)} 17 (2001) 341–349.
LibreCat
 
[57]
2001 | Misc | LibreCat-ID: 13096
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
H.-G. Liang, S. Hellebrand, H.-J. Wunderlich, Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST, IEEE European Test Workshop, Stockholm, Sweden, 2001.
LibreCat
 
[56]
2001 | Conference Paper | LibreCat-ID: 13004
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
H.-G. Liang, S. Hellebrand, H.-J. Wunderlich, in: {IEEE International Test Conference (ITC’01)}, {IEEE}, Baltimore, MD, USA, 2001, pp. 894–902.
LibreCat | DOI
 
[55]
2001 | Journal Article | LibreCat-ID: 13047
Deterministic BIST Scheme Based on Reseeding of Folding Counters
H.-G. Liang, S. Hellebrand, H.-J. Wunderlich, {Journal of Computer Research and Development, (Jisuanji Yanjiu Yu Fazhan)} 38 (2001) 931.
LibreCat
 
[54]
2000 | Misc | LibreCat-ID: 13094
Hardwarepraktikum im Diplomstudiengang Informatik
S. Hellebrand, H.-J. Wunderlich, Hardwarepraktikum Im Diplomstudiengang Informatik, Handbuch Lehre, Berlin, Raabe Verlag, 2000.
LibreCat
 
[53]
2000 | Misc | LibreCat-ID: 13095
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
S. Hellebrand, H.-G. Liang, H.-J. Wunderlich, A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters, IEEE European Test Workshop, Cascais, Portugal, 2000.
LibreCat
 
[52]
2000 | Conference Paper | LibreCat-ID: 13005
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
S. Hellebrand, H.-G. Liang, H.-J. Wunderlich, in: {IEEE International Test Conference (ITC’00)}, {IEEE}, Atlantic City, NJ, USA, 2000, pp. 778–784.
LibreCat | DOI
 
[51]
1999 | Conference Paper | LibreCat-ID: 13006
Error Detecting Refreshment for Embedded DRAMs
S. Hellebrand, H.-J. Wunderlich, A. A. Ivaniuk, Y. V. Klimets, V. N. Yarmolik, in: {17th IEEE VLSI Test Symposium (VTS’99)}, {IEEE (Comput. Soc.)}, Dana Point, CA, USA, 1999, pp. 384–390.
LibreCat | DOI
 
[50]
1999 | Book | LibreCat-ID: 13065
Selbsttestbare Steuerwerke - Strukturen und Syntheseverfahren
S. Hellebrand, Selbsttestbare Steuerwerke - Strukturen Und Syntheseverfahren, Verlag Dr. Kovac, Hamburg, Verlag Dr. Kovac, Hamburg, 1999.
LibreCat
 
[49]
1999 | Conference Paper | LibreCat-ID: 13066
Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms
V. N. Yarmolik, I. V. Bykov, S. Hellebrand, H.-J. Wunderlich, in: {Third European Dependable Computing Conference (EDCC-3)}, Prague, Czech Republic, 1999.
LibreCat
 
[48]
1999 | Conference Paper | LibreCat-ID: 13067
Symmetric Transparent BIST for RAMs
S. Hellebrand, H.-J. Wunderlich, V. N. Yarmolik, in: {Design, Automation and Test in Europe (DATE’99)}, Munich, Germany, 1999, pp. 702–707.
LibreCat
 
[47]
1999 | Misc | LibreCat-ID: 13093
Exploiting Symmetries to Speed Up Transparent BIST
S. Hellebrand, H.-J. Wunderlich, V. N. Yarmolik, Exploiting Symmetries to Speed Up Transparent BIST, 11th GI/ITG/GMM/IEEE Workshop, 1999.
LibreCat
 
[46]
1998 | Conference Paper | LibreCat-ID: 13063
New Transparent RAM BIST Based on Self-Adjusting Output Data Compression
V. N. Yarmolik, Y. V. Klimets, S. Hellebrand, H.-J. Wunderlich, in: {Design \& Diagnostics of Electronic Circuits \& Systems}, Szczyrk, Poland, 1998, pp. 27–33.
LibreCat
 
[45]
1998 | Conference Paper | LibreCat-ID: 13007
Fast Self-Recovering Controllers
A. Hertwig, S. Hellebrand, H.-J. Wunderlich, in: {16th IEEE VLSI Test Symposium (VTS’98)}, {IEEE (Comput. Soc.)}, Monterey, CA, USA, 1998, pp. 296–302.
LibreCat | DOI
 
[44]
1998 | Journal Article | LibreCat-ID: 13064
Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications
S. Hellebrand, A. Hertwig, H.-J. Wunderlich, {IEEE Design and Test} 15 (1998) 36–41.
LibreCat
 
[43]
1998 | Conference Paper | LibreCat-ID: 13008
Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs
S. Hellebrand, H.-J. Wunderlich, V. N. Yarmolik, in: {IEEE Design, Automation and Test in Europe (DATE’98)}, {IEEE (Comput.Soc)}, Paris, France, 1998, pp. 173–179.
LibreCat | DOI
 
[42]
1998 | Book Chapter | LibreCat-ID: 13060
Mixed-Mode BIST Using Embedded Processors
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, in: Mixed-Mode BIST Using Embedded Processors, {Kluwer Academic Publishers}, In: M. Nicolaidis, Y. Zorian, D. K. Pradhan (Eds.): On-Line Testing for VLSI, Boston: Kluwer Academic Publishers 1998, 1998.
LibreCat
 
[41]
1998 | Misc | LibreCat-ID: 13091
Efficient Consistency Checking for Embedded Memories
V. N. Yarmolik, S. Hellebrand, H.-J. Wunderlich, Efficient Consistency Checking for Embedded Memories, 5th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1998.
LibreCat
 
[40]
1998 | Journal Article | LibreCat-ID: 13061
Mixed-Mode BIST Using Embedded Processors
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, {Journal of Electronic Testing Theory and Applications - JETTA} 12 (1998) 127–138.
LibreCat
 
[39]
1998 | Misc | LibreCat-ID: 13092
Efficient Consistency Checking for Embedded Memories
V. N. Yarmolik, S. Hellebrand, H.-J. Wunderlich, Efficient Consistency Checking for Embedded Memories, 10th GI/ITG/GMM/IEEE Workshop, 1998.
LibreCat
 
[38]
1998 | Report | LibreCat-ID: 13029
Test und Synthese schneller eingebetteter Systeme
S. Hellebrand, H.-J. Wunderlich, Test Und Synthese Schneller Eingebetteter Systeme, Universität Stuttgart, 1998.
LibreCat
 
[37]
1997 | Misc | LibreCat-ID: 13090
Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications
A. Hertwig, S. Hellebrand, H.-J. Wunderlich, Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications, 3rd IEEE International On-Line Testing Workshop, Crete, Greece, 1997.
LibreCat
 
[36]
1997 | Misc | LibreCat-ID: 13089
STARBIST: Scan Autocorrelated Random Pattern Generation
K.-H. Tsai, S. Hellebrand, J. Rajski, M. Marek-Sadowska, STARBIST: Scan Autocorrelated Random Pattern Generation, 4th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1997.
LibreCat
 
[35]
1997 | Conference Paper | LibreCat-ID: 13009
STARBIST: Scan Autocorrelated Random Pattern Generation
K.-H. Tsai, S. Hellebrand, M. Marek-Sadowska, J. Rajski, in: {34th ACM/IEEE Design Automation Conference (DAC’97)}, {IEEE}, Anaheim, CA, USA, 1997.
LibreCat | DOI
 
[34]
1996 | Misc | LibreCat-ID: 13087
Using Embedded Processors for BIST
S. Hellebrand, H.-J. Wunderlich, Using Embedded Processors for BIST, 3rd IEEE International Test Synthesis Workshop, Santa Barbara, CA, 1996.
LibreCat
 
[33]
1996 | Misc | LibreCat-ID: 13088
Mixed-Mode BIST Using Embedded Processors
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, Mixed-Mode BIST Using Embedded Processors, 2nd IEEE International On-Line Testing Workshop. Biarritz, France, 1996.
LibreCat
 
[32]
1996 | Conference Paper | LibreCat-ID: 13010
Mixed-Mode BIST Using Embedded Processors
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, in: {IEEE International Test Conference (ITC’96)}, {IEEE}, Washington, DC, USA, 1996, pp. 195–204.
LibreCat | DOI
 
[31]
1995 | Report | LibreCat-ID: 13026
Synthesis Procedures for Self-Testable Controllers
S. Hellebrand, H.-J. Wunderlich, Synthesis Procedures for Self-Testable Controllers, University of Siegen, Germany, 1995.
LibreCat
 
[30]
1995 | Report | LibreCat-ID: 13027
Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis
S. Hellebrand, H.-J. Wunderlich, F. Goncalves, J. Paulo Teixeira, Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis, University Siegen, Germany, 1995.
LibreCat
 
[29]
1995 | Journal Article | LibreCat-ID: 13011
Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers
S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, B. Courtois, {IEEE Transactions on Computers} 44 (1995) 223–233.
LibreCat | DOI
 
[28]
1995 | Report | LibreCat-ID: 13028
Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing
S. Hellebrand, M. Herzog, H.-J. Wunderlich, Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing, University of Siegen, Germany, 1995.
LibreCat
 
[27]
1995 | Conference Paper | LibreCat-ID: 13012
Pattern Generation for a Deterministic BIST Scheme
S. Hellebrand, B. Reeb, S. Tarnick, H.-J. Wunderlich, in: {ACM/IEEE International Conference on Computer Aided Design (ICCAD’95)}, {IEEE (Comput. Soc. Press)}, San Jose, CA, USA, 1995, pp. 88–94.
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[26]
1995 | Misc | LibreCat-ID: 13086
Pattern Generation for a Deterministic BIST Scheme
S. Hellebrand, B. Reeb, S. Tarnick, H.-J. Wunderlich, Pattern Generation for a Deterministic BIST Scheme, 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA, 1995.
LibreCat
 
[25]
1994 | Conference Paper | LibreCat-ID: 13013
Synthesis of Self-Testable Controllers
S. Hellebrand, H.-J. Wunderlich, in: {European Design and Test Conference (EDAC/ETC/EUROASIC)}, {IEEE (Comput. Soc. Press)}, Paris, France, 1994, pp. 580–585.
LibreCat | DOI
 
[24]
1994 | Report | LibreCat-ID: 13025
Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time
S. Hellebrand, A. Juergensen, A. Stroele, H.-J. Wunderlich, Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time, University of Siegen, Germany, 1994.
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[23]
1994 | Conference Paper | LibreCat-ID: 13014
An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures
S. Hellebrand, H.-J. Wunderlich, in: {ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94)}, {IEEE}, San Jose, CA, USA, 1994, pp. 110–116.
LibreCat | DOI
 
[22]
1994 | Misc | LibreCat-ID: 13083
Effiziente Testsatzkodierung für Prüfpfad-basierte Selbsttestarchitekturen
S. Venkataraman, J. Rajski, S. Hellebrand, S. Tarnick, Effiziente Testsatzkodierung Für Prüfpfad-Basierte Selbsttestarchitekturen, 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands, 1994.
LibreCat
 
[21]
1994 | Misc | LibreCat-ID: 13084
Ein Verfahren zur testfreundlichen Steuerwerkssynthese
S. Hellebrand, H.-J. Wunderlich, Ein Verfahren Zur Testfreundlichen Steuerwerkssynthese, 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands, 1994.
LibreCat
 
[20]
1994 | Conference Paper | LibreCat-ID: 13059
Synthese schneller selbsttestbarer Steuerwerke
S. Hellebrand, H.-J. Wunderlich, in: {Tagungsband Der GI/GME/ITG-Fachtagung \& Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme}, Oberwiesenthal, Informatik Xpress 4, TU Chemnitz Zwickau, Germany, 1994, pp. 3–11.
LibreCat
 
[19]
1994 | Misc | LibreCat-ID: 13085
Synthesis for Testability - the ARCHIMEDES Approach
S. Hellebrand, J. Paulo Teixeira, H.-J. Wunderlich, Synthesis for Testability - the ARCHIMEDES Approach, 1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1994.
LibreCat
 
[18]
1994 | Report | LibreCat-ID: 13024
Synthesis for Off-line Testability
S. Hellebrand, A. Juergensen, H.-J. Wunderlich, Synthesis for Off-Line Testability, University of Siegen, Germany, 1994.
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[17]
1993 | Misc | LibreCat-ID: 13082
Synthesis of Self-Testable Controllers
S. Hellebrand, H.-J. Wunderlich, Synthesis of Self-Testable Controllers, ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support”, Montpellier, France, 1993.
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[16]
1993 | Conference Paper | LibreCat-ID: 13015
An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers
S. Venkataraman, J. Rajski, S. Hellebrand, S. Tarnick, in: {ACM/IEEE International Conference on Computer Aided Design (ICCAD’93)}, {IEEE (Comput. Soc. Press)}, 1993.
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[15]
1993 | Misc | LibreCat-ID: 13081
Effiziente Erzeugung deterministischer Muster im Selbsttest
S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, Effiziente Erzeugung Deterministischer Muster Im Selbsttest, 5th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Holzhau, Germany, 1993.
LibreCat
 
[14]
1992 | Misc | LibreCat-ID: 13076
Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs
S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs, IEEE Design for Testability Workshop, Vail, CO, USA, 1992.
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[13]
1992 | Conference Paper | LibreCat-ID: 13016
Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers
S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, in: {IEEE International Test Conference (ITC’92)}, {IEEE}, Baltimore, MD, USA, 1992, pp. 120–129.
LibreCat | DOI
 
[12]
1992 | Report | LibreCat-ID: 13023
Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs
S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs, Institut National Polytechnique de Grenoble, Grenoble, France, 1992.
LibreCat
 
[11]
1992 | Misc | LibreCat-ID: 13080
Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs
S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs, Workshop on New Directions for Testing, Montreal, Canada, 1992.
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[10]
1992 | Journal Article | LibreCat-ID: 13017
The Pseudoexhaustive Test of Sequential Circuits
H.-J. Wunderlich, S. Hellebrand, {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)} 11 (1992) 26–33.
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[9]
1991 | Book | LibreCat-ID: 13034
Synthese vollständig testbarer Schaltungen
S. Hellebrand, Synthese Vollständig Testbarer Schaltungen, Verlag Düsseldorf: VDI Verlag, Verlag Düsseldorf: VDI Verlag, 1991.
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[8]
1990 | Conference Paper | LibreCat-ID: 13018
Tools and Devices Supporting the Pseudo-Exhaustive Test
S. Hellebrand, H.-J. Wunderlich, in: {European Design Automation Conference (EDAC’90)}, {IEEE (Comput. Soc. Press)}, Glasgow, UK, 1990, pp. 13–17.
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[7]
1990 | Conference Paper | LibreCat-ID: 13019
Generating Pseudo-Exhaustive Vectors for External Testing
S. Hellebrand, H.-J. Wunderlich, O. F. Haberl, in: {IEEE International Test Conference (ITC’90)}, {IEEE (Comput. Soc. Press)}, Washington, DC, USA, 1990, pp. 670–679.
LibreCat | DOI
 
[6]
1990 | Misc | LibreCat-ID: 13103
Generating Pseudo-Exhaustive Vectors for External Testing
S. Hellebrand, H.-J. Wunderlich, O. F. Haberl, Generating Pseudo-Exhaustive Vectors for External Testing, IEEE Design for Testability Workshop, Vail, CO, USA, 1990.
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[5]
1989 | Conference Paper | LibreCat-ID: 13020
The Pseudo-Exhaustive Test of Sequential Circuits
H.-J. Wunderlich, S. Hellebrand, in: {IEEE International Test Conference (ITC’89)}, {IEEE (Comput. Soc. Press)}, Washington, DC, USA, 1989, pp. 19–27.
LibreCat | DOI
 
[4]
1988 | Conference Paper | LibreCat-ID: 13021
Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits
H.-J. Wunderlich, S. Hellebrand, in: {18th International Symposium on Fault-Tolerant Computing, FTCS-18}, {IEEE (Comput. Soc. Press)}, Tokyo, Japan, 1988, pp. 36–45.
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[3]
1988 | Conference Paper | LibreCat-ID: 13058
Integrated Tools for Automatic Design for Testability
D. Schmid, H.-J. Wunderlich, F. Feldbusch, S. Hellebrand, J. Holzinger, A. Kunzmann, in: {In: Tool Integration and Design Environments, F.J. Rammig (Editor)}, Amsterdam: Elsevier Science Publishers B.V.(North Holland), IFIP, Amsterdam, The Netherlands, 1988, pp. 233–258.
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[2]
1988 | Conference Paper | LibreCat-ID: 13062
Automatisierung des Entwurfs vollständig testbarer Schaltungen
S. Hellebrand, H.-J. Wunderlich, in: {GI - 18. Jahrestagung II, Hamburg, 1988, Informatik-Fachberichte 188}, Springer Verlag, Hamburg, Germany, 1988, pp. 145–159.
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[1]
1986 | Report | LibreCat-ID: 13022
Deformation dicker Punkte und Netze von Quadriken
S. Hellebrand, Deformation Dicker Punkte Und Netze von Quadriken, Universität Regensburg, Fakultät für Mathematik, Regensburg, Germany, 1986.
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