Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time
S. Hellebrand, A. Juergensen, A. Stroele, H.-J. Wunderlich, Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time, University of Siegen, Germany, 1994.
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Hellebrand, SybilleLibreCat 
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Juergensen, Arne;
Stroele, Albrecht;
Wunderlich, Hans-Joachim
;
Juergensen, Arne;
Stroele, Albrecht;
Wunderlich, Hans-JoachimDepartment
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Hellebrand S, Juergensen A, Stroele A, Wunderlich H-J. Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time. University of Siegen, Germany; 1994.
Hellebrand, S., Juergensen, A., Stroele, A., & Wunderlich, H.-J. (1994). Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time. University of Siegen, Germany.
@book{Hellebrand_Juergensen_Stroele_Wunderlich_1994, place={University of Siegen, Germany}, title={Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time}, author={Hellebrand, Sybille and Juergensen, Arne and Stroele, Albrecht and Wunderlich, Hans-Joachim}, year={1994} }
Hellebrand, Sybille, Arne Juergensen, Albrecht Stroele, and Hans-Joachim Wunderlich. Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time. University of Siegen, Germany, 1994.
S. Hellebrand, A. Juergensen, A. Stroele, and H.-J. Wunderlich, Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time. University of Siegen, Germany, 1994.
Hellebrand, Sybille, et al. Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time. 1994.
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