Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing

S. Hellebrand, M. Herzog, H.-J. Wunderlich, Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing, University of Siegen, Germany, 1995.

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Hellebrand S, Herzog M, Wunderlich H-J. Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing. University of Siegen, Germany; 1995.
Hellebrand, S., Herzog, M., & Wunderlich, H.-J. (1995). Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing. University of Siegen, Germany.
@book{Hellebrand_Herzog_Wunderlich_1995, place={University of Siegen, Germany}, title={Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing}, author={Hellebrand, Sybille and Herzog, Maik and Wunderlich, Hans-Joachim}, year={1995} }
Hellebrand, Sybille, Maik Herzog, and Hans-Joachim Wunderlich. Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing. University of Siegen, Germany, 1995.
S. Hellebrand, M. Herzog, and H.-J. Wunderlich, Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing. University of Siegen, Germany, 1995.
Hellebrand, Sybille, et al. Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing. 1995.

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