An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy

P. Oehler, S. Hellebrand, H.-J. Wunderlich, An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy, 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany, 2007.

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Oehler P, Hellebrand S, Wunderlich H-J. An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany; 2007.
Oehler, P., Hellebrand, S., & Wunderlich, H.-J. (2007). An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany.
@book{Oehler_Hellebrand_Wunderlich_2007, place={17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany}, title={An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy}, author={Oehler, Philipp and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2007} }
Oehler, Philipp, Sybille Hellebrand, and Hans-Joachim Wunderlich. An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany, 2007.
P. Oehler, S. Hellebrand, and H.-J. Wunderlich, An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany, 2007.
Oehler, Philipp, et al. An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. 2007.

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