Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits

B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: {4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper)}, Chicago, IL, USA, 2010.

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{4th Workshop on Dependable and Secure Nanocomputing (WDSN'10), (Invited Paper)}
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Becker B, Hellebrand S, Polian I, Straube B, Vermeiren W, Wunderlich H-J. Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. In: {4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper)}. Chicago, IL, USA; 2010.
Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., & Wunderlich, H.-J. (2010). Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. In {4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper)}. Chicago, IL, USA.
@inproceedings{Becker_Hellebrand_Polian_Straube_Vermeiren_Wunderlich_2010, place={Chicago, IL, USA}, title={Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits}, booktitle={{4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper)}}, author={Becker, Bernd and Hellebrand, Sybille and Polian, Ilia and Straube, Bernd and Vermeiren, Wolfgang and Wunderlich, Hans-Joachim}, year={2010} }
Becker, Bernd, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, and Hans-Joachim Wunderlich. “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits.” In {4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper)}. Chicago, IL, USA, 2010.
B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, and H.-J. Wunderlich, “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits,” in {4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper)}, 2010.
Becker, Bernd, et al. “Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits.” {4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper)}, 2010.

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