Analysis of PSSS modulation for optimization of DAC bit resolution for 100 Gbps systems

The terahertz frequency range provides abundant bandwidth (25GHz ~ 50 GHz) to achieve ultra-high-speed wireless communication and enables data rates up to and above 100 Gbps. We choose Parallel Sequence Spread Spectrum (PSSS) as an analog friendly modulation and coding scheme that allows for an efficient mixed-signal implementation of a 100 Gbps wireless communication system. In our system design, we require a DAC (Digital to Analog converters) running at 1.67 G symbols/sec. The optimization of the bit resolution of this DAC will considerably reduce the hardware implementation efforts. In this work, we presented the analytical model for PSSS modulation and deduced a mathematical formula to calculate the number of discrete level amplitudes along with their probability distribution appearing at the output of the PSSS modulated signal. The analytical analysis assists in predicting the number of the quantization level of the DAC needed at the PSSS transmitter. The theoretical analysis shows that there are in total 225 discrete levels at the output of the PSSS encoder which leads to an 8-bit resolution of DAC. In this paper, we analyzed the variation of BER (Bit Error Rate) to the clipping of low probability amplitude levels and found that there is an only slight increase of the BER when we clip off the low probability amplitude levels. Thus, there is a tradeoff involved in a minor growth of BER concerning the reduction of the DAC bit resolution. Finally, we can reduce the DAC bit resolution from 8 bits to 7 bits and thus simplify the hardware implementation efforts of DAC operating at 1.67 Gbps.