A UML Virtual Machine for Embedded Systems

StateCharts are well accepted for embedded systems specification for various applications. However, for the specification of complex systems they have several limitations. In this article, we present a novel approach to efficiently execute an UML 2.0 subset for embedded real- time systems implementation with focus on hardware interrupts, software exceptions, and timeouts. We introduce a UML Virtual Machine, which directly executes sequence diagrams, which are embedded into hierarchically structured state transition diagrams. Whereas state diagrams are directly executed as Embedded State Machines (ESMs), sequence diagrams are translated into UVM Bytecode. The final UVM execution is performed by the interaction of the ESM and the Bytecode Interpreter. Due to our completely model- based approach, the UVM runtime kernel is easily adaptable and scalable to different scheduling and memory management strategies.