AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference
G. Pape, B. Wintermann, L. Jungemann, M. Lass, M. Meyer, H. Riebler, C. Plessl, in: Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, n.d.
Download
No fulltext has been uploaded.
Conference Paper
| Accepted
| English
Author
Pape, Gerrit;
Wintermann, BjarneLibreCat 
;
Jungemann, LinusLibreCat ;
Lass, Michael;
Meyer, Marius;
Riebler, HeinrichLibreCat;
Plessl, ChristianLibreCat
;
Jungemann, LinusLibreCat ;
Lass, Michael;
Meyer, Marius;
Riebler, HeinrichLibreCat;
Plessl, ChristianLibreCat Publishing Year
Proceedings Title
Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies
Conference
The International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies 2025 (HEART 2025)
Conference Location
Kumamoto, Japan
Conference Date
2025-05-26 – 2025-05-28
LibreCat-ID
Cite this
Pape G, Wintermann B, Jungemann L, et al. AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference. In: Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies.
Pape, G., Wintermann, B., Jungemann, L., Lass, M., Meyer, M., Riebler, H., & Plessl, C. (n.d.). AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference. Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. The International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies 2025 (HEART 2025) , Kumamoto, Japan.
@inproceedings{Pape_Wintermann_Jungemann_Lass_Meyer_Riebler_Plessl, title={AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference}, booktitle={Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies}, author={Pape, Gerrit and Wintermann, Bjarne and Jungemann, Linus and Lass, Michael and Meyer, Marius and Riebler, Heinrich and Plessl, Christian} }
Pape, Gerrit, Bjarne Wintermann, Linus Jungemann, Michael Lass, Marius Meyer, Heinrich Riebler, and Christian Plessl. “AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference.” In Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, n.d.
G. Pape et al., “AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference,” presented at the The International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies 2025 (HEART 2025) , Kumamoto, Japan.
Pape, Gerrit, et al. “AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference.” Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies.
Google Scholar