A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids
L. Luchterhandt, V. Govindasamy, Y. Wang, C. Scheytt, W. Mueller, R. Dömer, in: 2025 Forum on Specification &Amp; Design Languages (FDL), IEEE, 2025.
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Luchterhandt, Lars;
Govindasamy, Vivek;
Wang, Yutong;
Scheytt, Christoph;
Mueller, Wolfgang;
Dömer, Rainer
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2025 Forum on Specification & Design Languages (FDL)
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Luchterhandt L, Govindasamy V, Wang Y, Scheytt C, Mueller W, Dömer R. A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids. In: 2025 Forum on Specification &Amp; Design Languages (FDL). IEEE; 2025. doi:10.1109/fdl68117.2025.11165408
Luchterhandt, L., Govindasamy, V., Wang, Y., Scheytt, C., Mueller, W., & Dömer, R. (2025). A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids. 2025 Forum on Specification &Amp; Design Languages (FDL). https://doi.org/10.1109/fdl68117.2025.11165408
@inproceedings{Luchterhandt_Govindasamy_Wang_Scheytt_Mueller_Dömer_2025, title={A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids}, DOI={10.1109/fdl68117.2025.11165408}, booktitle={2025 Forum on Specification & Design Languages (FDL)}, publisher={IEEE}, author={Luchterhandt, Lars and Govindasamy, Vivek and Wang, Yutong and Scheytt, Christoph and Mueller, Wolfgang and Dömer, Rainer}, year={2025} }
Luchterhandt, Lars, Vivek Govindasamy, Yutong Wang, Christoph Scheytt, Wolfgang Mueller, and Rainer Dömer. “A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids.” In 2025 Forum on Specification &Amp; Design Languages (FDL). IEEE, 2025. https://doi.org/10.1109/fdl68117.2025.11165408.
L. Luchterhandt, V. Govindasamy, Y. Wang, C. Scheytt, W. Mueller, and R. Dömer, “A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids,” 2025, doi: 10.1109/fdl68117.2025.11165408.
Luchterhandt, Lars, et al. “A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids.” 2025 Forum on Specification &Amp; Design Languages (FDL), IEEE, 2025, doi:10.1109/fdl68117.2025.11165408.
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