60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design
B. Sadiye, M. Iftekhar, W. Müller, J.C. Scheytt, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2025).
Download
No fulltext has been uploaded.
Journal Article
| Published
| English
Author
Publishing Year
Journal Title
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISSN
LibreCat-ID
Cite this
Sadiye B, Iftekhar M, Müller W, Scheytt JC. 60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Published online 2025. doi:10.1109/TVLSI.2025.3625787
Sadiye, B., Iftekhar, M., Müller, W., & Scheytt, J. C. (2025). 60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. https://doi.org/10.1109/TVLSI.2025.3625787
@article{Sadiye_Iftekhar_Müller_Scheytt_2025, title={60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design}, DOI={10.1109/TVLSI.2025.3625787}, journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, publisher={IEEE}, author={Sadiye, Babak and Iftekhar, Mohammed and Müller, Wolfgang and Scheytt, J. Christoph}, year={2025} }
Sadiye, Babak, Mohammed Iftekhar, Wolfgang Müller, and J. Christoph Scheytt. “60-Gb/s 1:4 Demultiplexer in 22-Nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2025. https://doi.org/10.1109/TVLSI.2025.3625787.
B. Sadiye, M. Iftekhar, W. Müller, and J. C. Scheytt, “60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2025, doi: 10.1109/TVLSI.2025.3625787.
Sadiye, Babak, et al. “60-Gb/s 1:4 Demultiplexer in 22-Nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2025, doi:10.1109/TVLSI.2025.3625787.
Google Scholar