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264 Publications


2017 | Conference Paper | LibreCat-ID: 24223
L. Wu, S. Abughannam, W. Müller, C. Scheytt, and W. Ecker, “SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study,” in 2nd Workshop on Resiliency in Embedded Electronic Systems (REES), 2017, p. 68.
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2017 | Conference Paper | LibreCat-ID: 24224
P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, and C. Scheytt, “ANALISA - A Tool for Static Instruction Set Analysis,” 2017.
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2017 | Conference Paper | LibreCat-ID: 24225
P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, and C. Scheytt, “An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries,” in 2nd Workshop on Resiliency in Embedded Electronic Systems (REES) , 2017, p. 44.
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2016 | Conference Paper | LibreCat-ID: 24264
P. Adelt, B. Koppelmann, W. Müller, M. Becker, B. Kleinjohann, and C. Scheytt, “Fast Dynamic Fault Injection for Virtual Microcontroller Platforms,” 2016, doi: 10.1109/VLSI-SoC.2016.7753545.
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2016 | Conference Paper | LibreCat-ID: 24263
S. Abughannam, L. Wu, W. Müller, C. Scheytt, W. Ecker, and C. Novello, “Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study,” 2016.
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2015 | Conference Paper | LibreCat-ID: 24289
W. Müller, L. Wu, C. Scheytt, M. Becker, and S. Schoenberg, “On the Correlation of HW Faults and SW Errors,” in Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014), 2015.
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2015 | Book (Editor) | LibreCat-ID: 53590
D. Müller-Gridschneder, W. Müller, and S. Mitra, Eds., Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems. Amsterdam, Netherlands, 2015.
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2014 | Conference Paper | LibreCat-ID: 25145
M. Becker, C. Kuznik, and W. Müller, “Virtual Platforms for Model-Based Design of Dependable Cyber-Physical System Software,” 2014.
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2014 | Conference Paper | LibreCat-ID: 25155
M. Becker, C. Kuznik, and W. Müller, “Fault Effect Modeling in a Heterogeneous SystemC Virtual Platform Framework for Cyber-Physical Systems,” 2014.
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2014 | Conference Paper | LibreCat-ID: 25161
B. Koppelmann, M. Becker, and W. Müller, “Portierung der TriCore-Architektur auf QEMU,” 2014.
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2014 | Conference Paper | LibreCat-ID: 24305
F. Mischkalla and W. Müller, “Architectural Low-Power Design Using Transaction-Based System Modeling and Simulation,” 2014, doi: 10.1109/SAMOS.2014.6893219.
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2014 | Journal Article | LibreCat-ID: 24302
B. Koppelmann, B. Messidat, M. Becker, C. Kuznik, W. Müller, and C. Scheytt, “Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU,” Design and Verification Conference (DVCON EUROPE), 2014.
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2014 | Journal Article | LibreCat-ID: 24309
C. Kuznik and W. Müller, “Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure,” Design, Automation and Test in Europe DATE, University Booth, Dresden, 2014.
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2014 | Conference Paper | LibreCat-ID: 24311
J.-H. Oetjens et al., “Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges,” 2014, doi: 10.1145/2593069.2602976.
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2014 | Conference Paper | LibreCat-ID: 25120
F. Mischkalla and W. Müller, “Architectural Low-Power Design Using Transaction-Based System Simulation,” Greece, Sep. 2014, IEEE, 2014.
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2014 | Conference Paper | LibreCat-ID: 25146
M. tech. M. M. Joy, W. Müller, and F.-J. Rammig, “Source code annotated memory leak detection for soft real time embedded systems with resource constraints,” 2014.
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2014 | Conference Paper | LibreCat-ID: 25144
F. Mischkalla and W. Müller, “Advanced SoC Virtual Prototyping for System-Level Power Planning and Validation,” 2014.
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2014 | Conference Paper | LibreCat-ID: 36918
M. Becker, C. Kuznik, and W. Müller, “Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems,” presented at the ACM/IEEE International Conference on Cyber-Physical Systems (ICCPS), Berlin, 2014, doi: 10.1109/ICCPS.2014.6843726.
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2014 | Conference Paper | LibreCat-ID: 36917
C. Kuznik, W. Müller, and G. B. Defo, “An Assisted Single Source Verification Metric Model Code Generation Methodology,” presented at the Proceedings of the Electronic System Level Synthesis Conference (ESLSyn), 2014.
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2014 | Conference Paper | LibreCat-ID: 25166
C. Kuznik and W. Müller, “Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM,” 2014.
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