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264 Publications
2023 | Conference Abstract | LibreCat-ID: 48961
Iftekhar, Mohammed, Harshan Gowda, Pascal Kneuper, Babak Sadiye, Wolfgang Müller, and Christoph Scheytt. “A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 Nm FD-SOI CMOS Technology.” In 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2023. https://doi.org/10.1109/BCICTS54660.2023.10310954.
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2022 | Conference Paper | LibreCat-ID: 29302
Ecker, Wolfgang, Peer Adelt, Wolfgang Müller, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, et al. “The Scale4Edge RISC-V Ecosystem.” In In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022), 2022.
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2021 | Conference Paper | LibreCat-ID: 32125
Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” In MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop. Munich, DE: VDE, 2021.
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2021 | Conference Paper | LibreCat-ID: 32132
Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “QEMU zur Simulation von Worst-Case-Ausführungszeiten.” In MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop. Munich, DE: VDE, 2021.
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2021 | Conference Paper | LibreCat-ID: 23992
Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” In Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021), 2021.
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2020 | Conference Paper | LibreCat-ID: 24027
Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures.” In MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop. Stuttgart, DE, 2020.
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2019 | Conference Paper | LibreCat-ID: 24058
Koppelmann, Bastian, Peer Adelt, Wolfgang Müller, and Christoph Scheytt. “RISC-V Extensions for Bit Manipulation Instructions.” In 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS). Rhodos, Griechenland, 2019. https://doi.org/10.1109/PATMOS.2019.8862170.
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2019 | Conference Paper | LibreCat-ID: 24060
Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “Analyse Sicherheitskritischer Software Für RISC-V Prozessoren.” In MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019). Kaiserslautern, DE, 2019.
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2019 | Conference Paper | LibreCat-ID: 24061
Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Christoph Scheytt, and Benedikt Driessen. “QEMU for Dynamic Memory Analysis of Security Sensitive Software.” In 2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019, 32–34. Florence, Italy, 2019.
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2019 | Journal Article | LibreCat-ID: 24063
Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “QEMU Support for RISC-V: Current State and Future Releases.” 2nd International Workshop on RISC-V Research Activities (Presentation) (2019).
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2019 | Book (Editor) | LibreCat-ID: 53596
Bringmann, Oliver, Wolfgang Ecker, Wolfgang Müller, and Daniel Müller-Gridschneder, eds. Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT. Florence, Italy, 2019.
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2018 | Journal Article | LibreCat-ID: 24194
Adelt, Peer, Bastian Koppelmann, and Wolfgang Müller. “Current and Future RISC-V Activities for Virtual Prototyping and Chip Design.” International Workshop on RISC-V Research Activities Presentation (2018).
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2018 | Conference Paper | LibreCat-ID: 24196
Wu, Liang, Mohammad Khizer Hussain, Saed Abughannam, Wolfgang Müller, Christoph Scheytt, and Wolfgang Ecker. “Analog Fault Simulation Automation at Schematic Level with Random Sampling Techniques.” In 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)) . Italy/Taormina: IEEE, 2018. https://doi.org/10.1109/DTIS.2018.8368549.
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2018 | Book (Editor) | LibreCat-ID: 53595
Bringmann, Oliver, Wolfgang Ecker, Wolfgang Müller, and Daniel Müller-Gridschneder, eds. Proceedings of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT. Dresden, Germany, 2018.
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2017 | Conference Paper | LibreCat-ID: 24220
Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Daniel Mueller-Gritschneder, Bernd Kleinjohann, and Christoph Scheytt. “Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen.” In Tagungsband des Wissenschaftsforums Intelligente Technische Systeme. Germany, Paderborn: Verlagsschriftenreihe des Heinz Nixdorf Instituts, 2017. https://doi.org/10.17619/UNIPB/1-93.
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2017 | Conference Paper | LibreCat-ID: 24223
Wu, Liang, Saed Abughannam, Wolfgang Müller, Christoph Scheytt, and Wolfgang Ecker. “SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study.” In 2nd Workshop on Resiliency in Embedded Electronic Systems (REES), 68. Lausanne, Switzerland, 2017.
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2017 | Conference Paper | LibreCat-ID: 24224
Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Bernd Kleinjohann, and Christoph Scheytt. “ANALISA - A Tool for Static Instruction Set Analysis.” In Design Automation and Testing in Europe (DATE), University Booth Interactive Presentation. Lausanne, CH, 2017.
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2017 | Conference Paper | LibreCat-ID: 24225
Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Bernd Kleinjohann, and Christoph Scheytt. “An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries.” In 2nd Workshop on Resiliency in Embedded Electronic Systems (REES) , 44. Lausanne, Switzerland, 2017.
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2016 | Conference Paper | LibreCat-ID: 24264
Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Markus Becker, Bernd Kleinjohann, and Christoph Scheytt. “Fast Dynamic Fault Injection for Virtual Microcontroller Platforms.” In Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC). Tallin, Estonia, 2016. https://doi.org/10.1109/VLSI-SoC.2016.7753545.
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2016 | Conference Paper | LibreCat-ID: 24263
Abughannam, Saed, Liang Wu, Wolfgang Müller, Christoph Scheytt, Wolfgang Ecker, and Christiano Novello. “Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study.” In Analog 2016 - VDE, 2016.
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