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285 Publications
2026 | Conference Paper | LibreCat-ID: 63758
Hannemann, Kai Arne, Lars Luchterhandt, Wolfgang Müller, Markus Ulbricht, and Li Lu. “Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations.” In 38. ITG / GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen. Potsdam, 2026.
LibreCat
2026 | Conference Paper | LibreCat-ID: 65595
Hannemann, Kai Arne, Lars Markus Luchterhandt, Wolfgang Müller, Markus Ulbricht, Li Lu, and J. Christoph Scheytt. “TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture.” In 29. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2026), 2026.
LibreCat
2025 | Conference Paper | LibreCat-ID: 58861
Luchterhandt, Lars, Vivek Govindasamy, Yutong Wang, Rainer Dömer, Wolfgang Müller, and J. Christoph Scheytt. “Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells.” In OSSMPIC - Open Source Solutions for Massively Parallel Integrated Circuits. Lyon, France, 2025.
LibreCat
2025 | Journal Article | LibreCat-ID: 62148
Sadiye, Babak, Mohammed Iftekhar, Wolfgang Müller, and J. Christoph Scheytt. “60-Gb/s 1:4 Demultiplexer in 22-Nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2025. https://doi.org/10.1109/TVLSI.2025.3625787.
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2025 | Conference Paper | LibreCat-ID: 62126
Iftekhar, Mohammed, Babak Sadiye, Wolfgang Müller, and J. Christoph Scheytt. “A 50 Gbps Reference-Less NRZ Full-Rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 Nm SiGe:C BiCMOS Technology.” In IEEE Nordic Circuits and Systems Conference (NORCAS), 2025. https://doi.org/10.1109/NorCAS66540.2025.11231203.
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2025 | Conference Paper | LibreCat-ID: 58856
Hannemann, Kai Arne, Hüseyin Berke Bütün, Wolfgang Müller, and J. Christoph Scheytt. “Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study.” In MBMV 2025 - 28. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen. Warnemünde: VDE Verlag, 2025.
LibreCat
2024 | Conference Paper | LibreCat-ID: 53579
Palomero Bernardo, Paul, Patrick Schmid, Oliver Bringmann, Mohammed Iftekhar, Babak Sadiye, Wolfgang Müller, Andreas Koch, et al. “A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing.” In DATE 24 - Design Automation and Test in Europe, 2024.
LibreCat
2024 | Conference Paper | LibreCat-ID: 45778
Luchterhandt, Lars, Tom Nellius, Robert Beck, Rainer Dömer, Pascal Kneuper, Wolfgang Müller, and Babak Sadiye. “Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells.” In MBMV 2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“. VDE Verlag, 2024.
LibreCat
2023 | Conference Paper | LibreCat-ID: 45776
Ecker, Wolfgang, Milos Krstic, Markus Ulbricht, Andreas Mauderer, Eyck Jentzsch, Andreas Koch, Bastian Koppelmann, et al. “Scale4Edge – Scaling RISC-V for Edge Applications.” In RISC-V Summit Europe 2023, Barcelona, Spain, June 2023., 2023.
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2023 | Conference Paper | LibreCat-ID: 48530
Müller, Wolfgang, Markus Ulbricht, Lu Li, and Milos Krstic. “Der TETRISC SoC - Ein Resilientes Quad-Core System Auf Pulpissimo-Basis.” In 5. ITG / GMM / GI -Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen , 2023.
LibreCat
2023 | Conference Abstract | LibreCat-ID: 48961
Iftekhar, Mohammed, Harshan Gowda, Pascal Kneuper, Babak Sadiye, Wolfgang Müller, and Christoph Scheytt. “A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 Nm FD-SOI CMOS Technology.” In 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2023. https://doi.org/10.1109/BCICTS54660.2023.10310954.
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2023 | Conference Paper | LibreCat-ID: 45775
Luchterhandt, Lars, Tom Nellius, Robert Beck, Rainer Dömer, Pascal Kneuper, Wolfgang Müller, and Babak Sadiye. “Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture.” In MBMV 2023 - 26. Workshop "Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg. VDE Verlag, 2023.
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2023 | Conference Abstract | LibreCat-ID: 47064
Iftekhar, Mohammed, Harshan Nagaraju, Pascal Kneuper, Babak Sadiye, Wolfgang Müller, and J. Christoph Scheytt. “A 28-Gb/s 27.2 MW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 Nm FD-SOI CMOS Technology .” In BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2023.
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2022 | Conference Paper | LibreCat-ID: 29302
Ecker, Wolfgang, Peer Adelt, Wolfgang Müller, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, et al. “The Scale4Edge RISC-V Ecosystem.” In In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022), 2022.
LibreCat
2021 | Conference Paper | LibreCat-ID: 32125
Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” In MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop. Munich, DE: VDE, 2021.
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2021 | Conference Paper | LibreCat-ID: 32132
Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “QEMU zur Simulation von Worst-Case-Ausführungszeiten.” In MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop. Munich, DE: VDE, 2021.
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2021 | Conference Paper | LibreCat-ID: 23992
Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” In Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021), 2021.
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2020 | Conference Paper | LibreCat-ID: 24027
Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures.” In MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop. Stuttgart, DE, 2020.
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2019 | Conference Paper | LibreCat-ID: 24058
Koppelmann, Bastian, Peer Adelt, Wolfgang Müller, and Christoph Scheytt. “RISC-V Extensions for Bit Manipulation Instructions.” In 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS). Rhodos, Griechenland, 2019. https://doi.org/10.1109/PATMOS.2019.8862170.
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2019 | Conference Paper | LibreCat-ID: 24060
Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, and Christoph Scheytt. “Analyse Sicherheitskritischer Software Für RISC-V Prozessoren.” In MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019). Kaiserslautern, DE, 2019.
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