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285 Publications
2026 | Conference Paper | LibreCat-ID: 63758
K. A. Hannemann, L. Luchterhandt, W. Müller, M. Ulbricht, and L. Lu, “Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations,” presented at the 38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Potsdam, 2026.
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2026 | Conference Paper | LibreCat-ID: 65595
K. A. Hannemann, L. M. Luchterhandt, W. Müller, M. Ulbricht, L. Lu, and J. C. Scheytt, “TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture,” presented at the 29. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2026), Würzburg, 2026.
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2025 | Conference Paper | LibreCat-ID: 58861
L. Luchterhandt, V. Govindasamy, Y. Wang, R. Dömer, W. Müller, and J. C. Scheytt, “Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells,” 2025.
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2025 | Journal Article | LibreCat-ID: 62148
B. Sadiye, M. Iftekhar, W. Müller, and J. C. Scheytt, “60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2025, doi: 10.1109/TVLSI.2025.3625787.
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| DOI
2025 | Conference Paper | LibreCat-ID: 62126
M. Iftekhar, B. Sadiye, W. Müller, and J. C. Scheytt, “A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology,” presented at the IEEE Nordic Circuits and Systems Conference (NORCAS), Riga, Latvia, 2025, doi: 10.1109/NorCAS66540.2025.11231203.
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2025 | Conference Paper | LibreCat-ID: 58856
K. A. Hannemann, H. B. Bütün, W. Müller, and J. C. Scheytt, “Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study,” 2025.
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2024 | Conference Paper | LibreCat-ID: 53579
P. Palomero Bernardo et al., “A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing,” Valencia, Spain, 2024.
LibreCat
2024 | Conference Paper | LibreCat-ID: 45778
L. Luchterhandt et al., “Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells,” presented at the MBMV 2023 - 26. Workshop, Freiburg, , Germany, Freiburg, 2024.
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2023 | Conference Paper | LibreCat-ID: 45776
W. Ecker et al., “Scale4Edge – Scaling RISC-V for Edge Applications,” presented at the RISC-V Summit Europe 2023, Barcelona, Spain, June 2023., Barcelona, Spain, 2023.
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2023 | Conference Paper | LibreCat-ID: 48530
W. Müller, M. Ulbricht, L. Li, and M. Krstic, “Der TETRISC SoC - Ein resilientes Quad-Core System auf Pulpissimo-Basis,” presented at the 5. ITG / GMM / GI -Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen , Erfurt. Germany, 2023.
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2023 | Conference Abstract | LibreCat-ID: 48961
M. Iftekhar, H. Gowda, P. Kneuper, B. Sadiye, W. Müller, and C. Scheytt, “A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology,” presented at the 2023 IEEE BiCMOS und Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), Monterey, CA, USA, 2023, doi: 10.1109/BCICTS54660.2023.10310954.
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| DOI
2023 | Conference Paper | LibreCat-ID: 45775
L. Luchterhandt et al., “Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture,” presented at the MBMV 2023, Freiburg, Freiburg, 2023.
LibreCat
2023 | Conference Abstract | LibreCat-ID: 47064
M. Iftekhar, H. Nagaraju, P. Kneuper, B. Sadiye, W. Müller, and J. C. Scheytt, “A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology ,” MONTEREY, CALIFORNIA, USA, 2023.
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2022 | Conference Paper | LibreCat-ID: 29302
W. Ecker et al., “The Scale4Edge RISC-V Ecosystem,” 2022.
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2021 | Conference Paper | LibreCat-ID: 32125
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules,” 2021.
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| Files available
2021 | Conference Paper | LibreCat-ID: 32132
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “QEMU zur Simulation von Worst-Case-Ausführungszeiten,” 2021.
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2021 | Conference Paper | LibreCat-ID: 23992
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules,” 2021.
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2020 | Conference Paper | LibreCat-ID: 24027
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures,” 2020.
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2019 | Conference Paper | LibreCat-ID: 24058
B. Koppelmann, P. Adelt, W. Müller, and C. Scheytt, “RISC-V Extensions for Bit Manipulation Instructions,” 2019, doi: 10.1109/PATMOS.2019.8862170.
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| DOI
2019 | Conference Paper | LibreCat-ID: 24060
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Analyse sicherheitskritischer Software für RISC-V Prozessoren,” 2019.
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| Files available