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285 Publications
2026 | Conference Paper | LibreCat-ID: 63758
Hannemann, Kai Arne, et al. “Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations.” 38. ITG / GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen, 2026.
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2026 | Conference Paper | LibreCat-ID: 65595
Hannemann, Kai Arne, et al. “TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture.” 29. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2026), 2026.
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2025 | Conference Paper | LibreCat-ID: 58861
Luchterhandt, Lars, et al. “Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells.” OSSMPIC - Open Source Solutions for Massively Parallel Integrated Circuits, 2025.
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2025 | Journal Article | LibreCat-ID: 62148
Sadiye, Babak, et al. “60-Gb/s 1:4 Demultiplexer in 22-Nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2025, doi:10.1109/TVLSI.2025.3625787.
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2025 | Conference Paper | LibreCat-ID: 62126
Iftekhar, Mohammed, et al. “A 50 Gbps Reference-Less NRZ Full-Rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 Nm SiGe:C BiCMOS Technology.” IEEE Nordic Circuits and Systems Conference (NORCAS), 2025, doi:10.1109/NorCAS66540.2025.11231203.
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2025 | Conference Paper | LibreCat-ID: 58856
Hannemann, Kai Arne, et al. “Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study.” MBMV 2025 - 28. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen, VDE Verlag, 2025.
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2024 | Conference Paper | LibreCat-ID: 53579
Palomero Bernardo, Paul, et al. “A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing.” DATE 24 - Design Automation and Test in Europe, 2024.
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2024 | Conference Paper | LibreCat-ID: 45778
Luchterhandt, Lars, et al. “Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells.” MBMV 2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, VDE Verlag, 2024.
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2023 | Conference Paper | LibreCat-ID: 45776
Ecker, Wolfgang, et al. “Scale4Edge – Scaling RISC-V for Edge Applications.” RISC-V Summit Europe 2023, Barcelona, Spain, June 2023., 2023.
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2023 | Conference Paper | LibreCat-ID: 48530
Müller, Wolfgang, et al. “Der TETRISC SoC - Ein Resilientes Quad-Core System Auf Pulpissimo-Basis.” 5. ITG / GMM / GI -Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen , 2023.
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2023 | Conference Abstract | LibreCat-ID: 48961
Iftekhar, Mohammed, et al. “A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 Nm FD-SOI CMOS Technology.” 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2023, doi:10.1109/BCICTS54660.2023.10310954.
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2023 | Conference Paper | LibreCat-ID: 45775
Luchterhandt, Lars, et al. “Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture.” MBMV 2023 - 26. Workshop "Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg, VDE Verlag, 2023.
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2023 | Conference Abstract | LibreCat-ID: 47064
Iftekhar, Mohammed, et al. “A 28-Gb/s 27.2 MW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 Nm FD-SOI CMOS Technology .” BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2023.
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2022 | Conference Paper | LibreCat-ID: 29302
Ecker, Wolfgang, et al. “The Scale4Edge RISC-V Ecosystem.” In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022), 2022.
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2021 | Conference Paper | LibreCat-ID: 32125
Adelt, Peer, et al. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, VDE, 2021.
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2021 | Conference Paper | LibreCat-ID: 32132
Adelt, Peer, et al. “QEMU zur Simulation von Worst-Case-Ausführungszeiten.” MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, VDE, 2021.
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2021 | Conference Paper | LibreCat-ID: 23992
Adelt, Peer, et al. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021), 2021.
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2020 | Conference Paper | LibreCat-ID: 24027
Adelt, Peer, et al. “A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures.” MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, 2020.
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2019 | Conference Paper | LibreCat-ID: 24058
Koppelmann, Bastian, et al. “RISC-V Extensions for Bit Manipulation Instructions.” 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2019, doi:10.1109/PATMOS.2019.8862170.
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2019 | Conference Paper | LibreCat-ID: 24060
Adelt, Peer, et al. “Analyse Sicherheitskritischer Software Für RISC-V Prozessoren.” MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019), 2019.
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