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9 Publications
2025 | Conference Paper | LibreCat-ID: 59218
Reimer JD, Holst S, Sadeghi-Kohan S, Wunderlich H-J, Hellebrand S. ThorSim: Throughput-Oriented Timing Simulation of FinFET Digital Circuits. In: To Appear: IEEE International Symposium of Electronics Design Automation (ISEDA’25), May 2025. ; 2025.
LibreCat
2024 | Misc | LibreCat-ID: 50284
Stiballe A, Reimer JD, Sadeghi-Kohan S, Hellebrand S. Modeling Crosstalk-Induced Interconnect Delay with Polynomial Regression. 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’24), Feb. 2024; 2024.
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2024 | Conference Paper | LibreCat-ID: 56014
Jafarzadeh H, Klemme F, Reimer JD, Amrouch H, Hellebrand S, Wunderlich H-J. Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing. In: In: IEEE International Test Conference (ITC’24), San Diego, CA, USA, November 2024. IEEE; 2024.
LibreCat
2023 | Conference Paper | LibreCat-ID: 46738
Sadeghi-Kohan S, Reimer JD, Hellebrand S, Wunderlich H-J. Optimizing the Streaming of Sensor Data with Approximate Communication. In: IEEE Asian Test Symposium (ATS’23), October 2023. ; 2023.
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2023 | Conference Paper | LibreCat-ID: 45830
Jafarzadeh H, Klemme F, Reimer JD, et al. Robust Pattern Generation for Small Delay Faults under Process Variations. In: IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023. IEEE; 2023.
LibreCat
2023 | Misc | LibreCat-ID: 35204
Ghazal A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. On Cryptography Effects on Interconnect Reliability. 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023; 2023.
LibreCat
2023 | Conference Paper | LibreCat-ID: 41875
Badran A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. Approximate Computing: Balancing Performance, Power, Reliability, and Safety. In: 28th IEEE European Test Symposium (ETS’23), May 2023. ; 2023.
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2020 | Conference Paper | LibreCat-ID: 19422
Sprenger A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020. ; 2020.
LibreCat
2020 | Conference Paper | LibreCat-ID: 19421
Holst S, Kampmann M, Sprenger A, et al. Logic Fault Diagnosis of Hidden Delay Defects. In: IEEE International Test Conference (ITC’20), November 2020. ; 2020.
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