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9931 Publications
2010 | Conference Paper | LibreCat-ID: 29496
Ober-Blöbaum, S., & Walther, A. (2010). Computation of derivatives for structure preserving optimal control using automatic differentiation. Proceedings of Applied Mathematics and Mechanics, 10(1), 585–586.
LibreCat
2010 | Conference Paper | LibreCat-ID: 29495
Flaßkamp, K., Ober-Blöbaum, S., & Kobilarov, M. (2010). Solving optimal control problems by using inherent dynamical properties. Proceedings of Applied Mathematics and Mechanics, 10(1), 577–578.
LibreCat
2010 | Conference Paper | LibreCat-ID: 12983
Hopsch, F., Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., & Wunderlich, H.-J. (2010). Variation-Aware Fault Modeling. 19th IEEE Asian Test Symposium (ATS’10), 87–93. https://doi.org/10.1109/ats.2010.24
LibreCat
| DOI
2010 | Conference Paper | LibreCat-ID: 12985
Indlekofer, T., Schnittger, M., & Hellebrand, S. (2010). Efficient Test Response Compaction for Robust BIST Using Parity Sequences. 28th IEEE International Conference on Computer Design (ICCD’10), 480–485. https://doi.org/10.1109/iccd.2010.5647648
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| DOI
2010 | Conference Paper | LibreCat-ID: 12986
Hunger, M., & Hellebrand, S. (2010). The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems. 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10), 101–108. https://doi.org/10.1109/dft.2010.19
LibreCat
| DOI
2010 | Conference Paper | LibreCat-ID: 12988
Froese, V., Ibers, R., & Hellebrand, S. (2010). Reusing NoC-Infrastructure for Test Data Compression. 28th IEEE VLSI Test Symposium (VTS’10), 227–231. https://doi.org/10.1109/vts.2010.5469570
LibreCat
| DOI
2010 | Conference Paper | LibreCat-ID: 13049
Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., & Wunderlich, H.-J. (2010). Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper).
LibreCat
2010 | Conference Paper | LibreCat-ID: 13050
Indlekofer, T., Schnittger, M., & Hellebrand, S. (2010). Robuster Selbsttest mit extremer Kompaktierung. 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 17–24.
LibreCat
2010 | Conference Paper | LibreCat-ID: 37007
Mischkalla, F., He, D., & Müller, W. (2010). Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems. Proceedings of DATE’10. 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden. https://doi.org/10.1109/DATE.2010.5456990
LibreCat
| DOI
2010 | Conference Paper | LibreCat-ID: 37009
Oliveira, M. F. S., Zabel, H., & Müller, W. (2010). Assertion-Based Verification of RTOS Properties. Proceedings of DATE’10. 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden. https://doi.org/10.1109/DATE.2010.5457130
LibreCat
| DOI
2010 | Conference Paper | LibreCat-ID: 37011
Klobedanz, K., Kuznik, C., Thuy, A., & Müller, W. (2010). Timing Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study. Proceedings of DATE’10, Dresden. 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden. https://doi.org/10.1109/DATE.2010.5457125
LibreCat
| DOI
2010 | Conference Paper | LibreCat-ID: 37037
Krupp, A., & Müller, W. (2010). A Systematic Approach to Combined HW/SW System Test. Proceedings of DATE’10. Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden. https://doi.org/10.1109/DATE.2010.5457186
LibreCat
| DOI
2010 | Conference Paper | LibreCat-ID: 37040
Becker, M., Di Guglielmo, G., Fummi, F., Müller, W., Pravadelli, G., & Xie, T. (2010). RTOS-Aware Refinement for TLM2.0-based HW/SW Design. Proceedings of DATE’10. Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden. https://doi.org/10.1109/DATE.2010.5456965
LibreCat
| DOI
2010 | Conference Paper | LibreCat-ID: 37046
Becker, M., Zabel, H., & Müller, W. (2010). A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement (L. Kleinjohann & B. Kleinjohann, Eds.). Springer Verlag. https://doi.org/10.1007/978-3-642-15234-4_15
LibreCat
| DOI
2010 | Conference Paper | LibreCat-ID: 37044
Klobedanz, K., Defo, G. B., Zabel, H., Müller, W., & Zhi, Y. (2010). Task Migration for Fault-Tolerant FlexRay Networks (L. Kleinjohann & B. Kleinjohann, Eds.). Springer Verlag. https://doi.org/10.1007/978-3-642-15234-4_7
LibreCat
| DOI
2010 | Conference Paper | LibreCat-ID: 37042
Mischkalla, F., Müller, W., & He, D. (2010). A UML Profile for SysML-Based Comodeling for Embedded Systems Simulation and Synthesis. Proceedings of the M-BED Workshop.
LibreCat
2010 | Conference Paper | LibreCat-ID: 37043
Bol, A., Müller, W., & Krupp, A. (2010). Eine strukturierte Methode zur Generierung von SystemVerilog-Testumgebungen aus textuellen Anforderungsbeschreibungen. Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV).
LibreCat
2010 | Conference Paper | LibreCat-ID: 37050
Müller, W., He, D., Mischkalla, F., Wegele, A., Larkham, A., Whiston, P., Penil, P., Villar, E., Mitas, N., Kritharidis, D., Azcarate, F., & Carballeda, M. (2010). The SATURN Approach to SysML-based HW/SW Codesign. Proceedings of the IEEE Computer Society Annual Symposium on VLSI. https://doi.org/10.1007/978-94-007-1488-5_9
LibreCat
| DOI
2010 | Conference Paper | LibreCat-ID: 37048
Müller, W., Bol, A., Krupp, A., & Lundkvist, O. (2010). Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems (L. Kleinjohann & B. Kleinjohann, Eds.). Springer Verlag. https://doi.org/10.1007/978-3-642-15234-4_9
LibreCat
| DOI
2010 | Conference Paper | LibreCat-ID: 37049
Xie, T., Letombe, F., & Müller, W. (2010). Mutation-Analysis Directed Constrained Random Verification (L. Kleinjohann & B. Kleinjohann, Eds.). Springer Verlag.
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