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165 Publications
2001 | Journal Article | LibreCat-ID: 13068
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
S. Hellebrand, H.-G. Liang, H.-J. Wunderlich, Journal of Electronic Testing - Theory and Applications (JETTA) 17 (2001) 341–349.
LibreCat
S. Hellebrand, H.-G. Liang, H.-J. Wunderlich, Journal of Electronic Testing - Theory and Applications (JETTA) 17 (2001) 341–349.
2000 | Misc | LibreCat-ID: 13094
Hardwarepraktikum im Diplomstudiengang Informatik
S. Hellebrand, H.-J. Wunderlich, Hardwarepraktikum Im Diplomstudiengang Informatik, Handbuch Lehre, Berlin, Raabe Verlag, 2000.
LibreCat
S. Hellebrand, H.-J. Wunderlich, Hardwarepraktikum Im Diplomstudiengang Informatik, Handbuch Lehre, Berlin, Raabe Verlag, 2000.
2000 | Misc | LibreCat-ID: 13095
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
S. Hellebrand, H.-G. Liang, H.-J. Wunderlich, A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters, IEEE European Test Workshop, Cascais, Portugal, 2000.
LibreCat
S. Hellebrand, H.-G. Liang, H.-J. Wunderlich, A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters, IEEE European Test Workshop, Cascais, Portugal, 2000.
2000 | Conference Paper | LibreCat-ID: 13005
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
S. Hellebrand, H.-G. Liang, H.-J. Wunderlich, in: IEEE International Test Conference (ITC’00), IEEE, Atlantic City, NJ, USA, 2000, pp. 778–784.
LibreCat
| DOI
S. Hellebrand, H.-G. Liang, H.-J. Wunderlich, in: IEEE International Test Conference (ITC’00), IEEE, Atlantic City, NJ, USA, 2000, pp. 778–784.
1999 | Book | LibreCat-ID: 13065
Selbsttestbare Steuerwerke - Strukturen und Syntheseverfahren
S. Hellebrand, Selbsttestbare Steuerwerke - Strukturen Und Syntheseverfahren, Verlag Dr. Kovac, Hamburg, Verlag Dr. Kovac, Hamburg, 1999.
LibreCat
S. Hellebrand, Selbsttestbare Steuerwerke - Strukturen Und Syntheseverfahren, Verlag Dr. Kovac, Hamburg, Verlag Dr. Kovac, Hamburg, 1999.
1999 | Misc | LibreCat-ID: 13093
Exploiting Symmetries to Speed Up Transparent BIST
S. Hellebrand, H.-J. Wunderlich, V. N. Yarmolik, Exploiting Symmetries to Speed Up Transparent BIST, 11th GI/ITG/GMM/IEEE Workshop, 1999.
LibreCat
S. Hellebrand, H.-J. Wunderlich, V. N. Yarmolik, Exploiting Symmetries to Speed Up Transparent BIST, 11th GI/ITG/GMM/IEEE Workshop, 1999.
1999 | Conference Paper | LibreCat-ID: 13006
Error Detecting Refreshment for Embedded DRAMs
S. Hellebrand, H.-J. Wunderlich, A. A. Ivaniuk, Y. V. Klimets, V. N. Yarmolik, in: 17th IEEE VLSI Test Symposium (VTS’99), IEEE, Dana Point, CA, USA, 1999, pp. 384–390.
LibreCat
| DOI
S. Hellebrand, H.-J. Wunderlich, A. A. Ivaniuk, Y. V. Klimets, V. N. Yarmolik, in: 17th IEEE VLSI Test Symposium (VTS’99), IEEE, Dana Point, CA, USA, 1999, pp. 384–390.
1999 | Conference Paper | LibreCat-ID: 13066
Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms
V. N. Yarmolik, I. V. Bykov, S. Hellebrand, H.-J. Wunderlich, in: Third European Dependable Computing Conference (EDCC-3), Prague, Czech Republic, 1999.
LibreCat
V. N. Yarmolik, I. V. Bykov, S. Hellebrand, H.-J. Wunderlich, in: Third European Dependable Computing Conference (EDCC-3), Prague, Czech Republic, 1999.
1999 | Conference Paper | LibreCat-ID: 13067
Symmetric Transparent BIST for RAMs
S. Hellebrand, H.-J. Wunderlich, V. N. Yarmolik, in: Design Automation and Test in Europe (DATE’99), Munich, Germany, 1999, pp. 702–707.
LibreCat
S. Hellebrand, H.-J. Wunderlich, V. N. Yarmolik, in: Design Automation and Test in Europe (DATE’99), Munich, Germany, 1999, pp. 702–707.
1998 | Report | LibreCat-ID: 13029
Test und Synthese schneller eingebetteter Systeme
S. Hellebrand, H.-J. Wunderlich, Test Und Synthese Schneller Eingebetteter Systeme, Universität Stuttgart, 1998.
LibreCat
S. Hellebrand, H.-J. Wunderlich, Test Und Synthese Schneller Eingebetteter Systeme, Universität Stuttgart, 1998.